Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-05-30
2003-10-21
Cao, Phat X. (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S303000, C438S305000, C438S306000
Reexamination Certificate
active
06635538
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to an improvement technique for effectively taking advantage of an LDD (Lightly Doped Drain) structure.
2. Description of the Background Art
FIG. 29
is a front cross section showing a structure of a semiconductor device in the background art. A device
151
of this figure comprises a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and the MOSFET has an LDD (Lightly Doped Drain) structure. In this specification, according to the custom of this art, a transistor is referred to as MOSFET also when its gate electrode is not made of metal.
A semiconductor substrate
150
comprises a p-type well
61
. A device isolation layer
64
is selectively buried in a major surface of the semiconductor substrate
150
. Further, a pair of n
+
-type high-concentration semiconductor layers
62
and a shallower pair of n
−
-type low-concentration semiconductor layers
63
are selectively formed in a portion of the major surface of the semiconductor substrate
150
between the two device isolation layers
64
. Respective ones of the paired low-concentration semiconductor layers
63
are formed as if extending off respective ones of the paired high-concentration semiconductor layers
62
towards a portion of the major surface between the paired high-concentration semiconductor layers
62
.
In other words, the high-concentration semiconductor layers
62
and the low-concentration semiconductor layers
63
form an LDD structure. The high-concentration semiconductor layers
62
and the low-concentration semiconductor layers
63
correspond to source/drain regions of the MOSFET. An exposed surface layer of the well
61
between the paired high-concentration semiconductor layers
62
corresponds to a channel region CH of the MOSFET.
An insulating film
65
which is a silicon oxide film formed on the major surface of the semiconductor substrate
150
, and a gate electrode
67
is so formed as to face the channel region CH on the insulating film
65
. An insulating layer
68
is formed on the gate electrode
67
. Sidewalls
70
are formed on the sides of the gate electrode
67
and the insulating layer
68
.
An insulating layer
71
is so formed as to cover the above-described structure formed above the semiconductor substrate
150
. In the insulating layer
71
, a pair of contact holes
72
are selectively formed immediately above the pair of high-concentration semiconductor layers
62
. Each of the contact holes
72
is filled with a conductive main electrode
73
, and a pair of main electrodes
73
are thereby connected to the pair of high-concentration semiconductor layers
62
, respectively. An interconnection layer
74
is placed on the insulating layer
71
to be connected to the main electrode
73
.
Since the device
151
comprising the MOSFET has the above LDD structure, it is possible to relieve an electric field concentration that takes place in a pn junction between the well
61
and the semiconductor layers
62
and
63
. As a result, a hot-carrier effect is suppressed and that increases the lifetime and reliability of the insulating film
65
. Further, relieving the electric field concentration in the pn junction suppresses a leak current.
The background-art device
151
, however, has a problem that the advantage of the LDD structure can not be fully taken in some cases due to the problematic manufacturing process.
FIGS. 30
to
34
are process illustrations showing a method of manufacturing the device
151
. The process begins with a step of FIG.
30
.
In the step of
FIG. 30
, the semiconductor substrate
150
is prepared. In the major surface of the semiconductor substrate
150
, the p-type well
61
is formed and the device isolation layer
64
is selectively buried therein. By thermal oxidation, the insulating film
76
is formed as a thermal oxide film on the major surface of the semiconductor substrate
150
and thereafter the gate electrode
67
and the insulating layer
68
are formed on the insulating film
76
.
Next, as shown in
FIG. 31
, a pair of low-concentration semiconductor layers
63
are selectively formed. To form the low-concentration semiconductor layers
63
, an n-type impurity is selectively implanted into the major surface of the semiconductor substrate
150
by using the gate electrode
67
and the insulating layer
68
as a mask and then diffused.
As shown in
FIG. 32
, the sidewalls
70
are formed of silicon oxide. A material of the sidewalls
70
is so deposited as to entirely cover an exposed surface above the semiconductor substrate
150
and then the deposited material is selectively removed by RIE (Reactive Ion Etching), to form the sidewalls
70
by such a self-alignment process. In this process, only a portion of the insulating film
76
covered with the gate electrode
67
and the sidewalls
70
is left as the insulating film
65
.
After that, as shown in
FIG. 33
, a pair of high-concentration semiconductor layers
62
are selectively formed in the major surface of the semiconductor substrate
150
. To form the high-concentration semiconductor layers
62
, an n-type impurity is selectively implanted into the major surface of the semiconductor substrate
150
by using the gate electrode
67
, the insulating layer
68
and the sidewalls
70
as a mask and then diffused.
Next, a step of
FIG. 34
is executed. In the step of
FIG. 34
, a material of the insulating layer
71
is so deposited as to entirely cover an exposed surface above the semiconductor substrate
150
. After that, contact holes
72
are formed in the deposited material. Referring back to
FIG. 29
, the contact holes
72
are each filled with a conductive material, to form the main electrodes
73
. The interconnection layer
74
is so placed on the insulating layer
71
as to be connected to the main electrode
73
. Through the above steps, the device
151
is completed.
Among the above manufacturing process steps, the step of
FIG. 32
for forming the sidewalls
70
causes the problem of losing advantage of the LDD structure. This is illustrated in FIG.
35
. As shown in
FIG. 35
, the major surface of the semiconductor substrate
150
is also etched in some cases in a step of anisotropic etching using RIE.
This is caused by forming the insulating film
65
with thickness of only about 7 to 8 nm when the gate electrode
67
has a width of e.g., 0.15 &mgr;m, which is a typical value, (along the channel length, i.e., from one of the paired low-concentration semiconductor layers
63
to the other). When the major surface of the semiconductor substrate
150
is etched, as indicated by the sign “A” of
FIG. 35
, the edge of the high-concentration semiconductor layer
62
is not fully covered with the low-concentration semiconductor layer
63
. As a result, an electric field concentration occurs in the pn junction represented by the sign “A” and the hot-carrier effect is increased. Further, the electric field concentration in the pn junction increases a leak current. As a result, the advantage of using the LDD structure is reduced.
With size reduction of devices, the source/drain region of the MOSFET becomes shallower. Therefore, as devices are downsized more and more, the ill effect of etching damage on the semiconductor substrate
150
in formation of the sidewalls becomes more pronounced.
SUMMARY OF THE INVENTION
The present invention is directed to a semiconductor device. According to a first aspect of the present invention, the semiconductor device comprises: a semiconductor substrate comprising a major surface of a first conductivity type, a pair of low-concentration semiconductor layers of a second conductivity type selectively formed in the major surface separately from each other and a pair of high-concentration semiconductor layers of the second conductivity type selectively formed in the major surface separately from each other, having opposed edges recessed from opposed edges of the pair of
Morihara Toshinori
Tanaka Yoshinori
Cao Phat X.
Doan Theresa T.
Mitsubishi Denki & Kabushiki Kaisha
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