Method of manufacturing a semiconductor device

Details Method of manufacturing a semiconductor device Method of manufacturing a semiconductor device

2002-10-17

2003-07-22

Nguyen, Tuan H. (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S255000, C438S398000

Reexamination Certificate

active

06596582

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor devices such as dynamic random access memories (DRAMs) having a capacitor and methods of manufacturing the same and particularly to those having a rough surface to increase the capacitance of a capacitor and also enhancing a margin preventing the short-circuit between capacitors.
2. Description of the Background Art
FIGS. 26-34
show a method of forming in a conventional DRAM an upper portion of a storage node of a stacked, cylindrical capacitor that has a rough surface. Note that an underlying region including a semiconducting active region, an underlying wiring and the like is not shown. In the conventional method of forming an upper portion of a storage node, initially, as shown in
FIG. 26
, a resist mask
103
is placed on an interlayer insulating film
101
formed of tetra-ethyl-ortho-silicate (TEOS) and a storage node contact hole
102
is thus opened in the interlayer insulating film. Then, resist
103
is ashed and thus removed. Then, as shown in
FIG. 27
, phosphorus doped amorphous silicon
104
is deposited to fill storage node contact hole
102
. An underlying wiring and a storage node capacitor are connected by a plug interconnection of phosphorus doped amorphous silicon because phosphorus as a dopant can facilitate reduction in resistance and can readily be controlled. The amount of phosphorus doped is approximately 4 to 8×10
20
/cm
3
. The film has a thickness of approximately 0.1 to 0.2 &mgr;m, although it depends on the diameter of the storage node contact hole. Then, as shown in
FIG. 28
, the entire surface is anisotropically etched to remove the phosphorus doped amorphous silicon on the interlayer insulating film to leave the phosphorus doped amorphous silicon only in storage node contact hole
102
. Then, a plug interconnection
104
a
is formed. Then, as shown in
FIG. 29
, a phosphorus doped, polycrystalline silicon film
105
is deposited and boro-phospho-tetra-ethyl-ortho-silicate (BPTEOS)
106
is then deposited. Phosphorus doped, polycrystalline silicon film
105
has a thickness of approximately 0.05 to 0.1 &mgr;m. Then, as shown in
FIG. 30
, a resist mask (not shown) is used to etch BPTEOS
106
to form a pattern
106
a
of a storage node
107
. Then, a combination of the resist mask and BPTOES
106
a
etched as above is used as a mask to etch a phosphorus doped, polycrystalline silicon film
105
to form a lower portion
105
a
of the storage node. At this stage, storage nodes
107
partially formed are spaced by a spacing
110
. The geometry between storage nodes
107
is similar to various holes etched, providing an opening wider as it approaches the top, i.e., tapering toward the bottom. Then, as shown in
FIG. 31
, a non-doped amorphous silicon film
108
is deposited to later configure an upper portion of the storage node. Storage nodes
107
once separated at the
FIG. 30
step are connected together at the
FIG. 31
step. Non-doped amorphous silicon film
108
has a thickness of approximately 0.05 &mgr;m. Then, to separate storage nodes
107
from each other, non-doped amorphous silicon film
108
has an entire surface anisotropically etched. Thus, the non-doped amorphous silicon film covering a top surface of geometry
106
a
of the storage node is also etched away and BPTEOS
106
a
is exposed (FIG.
32
). Furthermore, the non-doped amorphous silicon film covering interlayer insulating film
101
between the storage nodes is also etched away, TEOS
101
of the interlayer insulating film is exposed, and storage nodes
107
are separated from each other by a spacing
110
a
(FIG.
32
). Then, vapor-phase HF is employed to selectively etch BPTEOS
106
a
filling the cylindrical, non-doped amorphous silicon. Thus a framework
108
a
of an upper, cylindrical portion of the storage node is formed.
As micro-fabrication technology further advances, cylindrical surface areas cannot provide a capacitor with a sufficient capacitance and accordingly there is a demand for further increased surface areas. To satisfy the demand, the cylindrical surface as described above is roughened to provide an increased capacitance to accommodate microfabrication. A conventional process for providing a rough surface employs a method of selectively roughening a cylindrical surface. In this method, Si
2
H
6
is initially introduced into a vacuum of approximately 700° C. and 10
−6
to 10
−8
Torr and an intermediate product obtained at the
FIG. 33
stage is placed in the flow of Si
2
H
6
for a predetermined period of time to allow a silicon seed to adhere to the cylinder of a storage node. Si
2
H
6
can be introduced for a period of time adjusted to prevent the silicon seed from adhering to TEOS
101
of the underlying interlayer insulating film. This process exploits the fact that depending on what the silicon seed adheres to the silicon seed has different incubation periods of time and has a shorter incubation period when it adheres to silicon than to oxide film. Then the product is annealed at approximately 700° C. and the silicon seed adhering to the cylindrical, non-doped amorphous silicon receives silicon atom from non-doped amorphous silicon
8
and is thus grown to stick out from the surface. Since a protrusion is grown on the surface from the silicon seed adhering to the surface, recesses and protrusions result, as seen across the entire surface, to roughen the surface (FIG.
34
). The silicon seed hardly adheres to any locations other than cylindrical, non-doped amorphous silicon
108
a
and the roughening is thus limited. Consequently, only cylindrical, non-doped amorphous silicon
108
a
has a surface selectively roughened to form upper portion
108
b
of the storage node having a rough surface.
If the storage node has upper portion
108
b
remaining as non-doped amorphous silicon, the capacitor depletes. To prevent this, the surface roughening process described above is followed by introducing PH
3
to dope the non-doped amorphous silicon with phosphorus; if phosphorus-doped amorphous silicon, rather than non-doped amorphous silicon, is initially used, the phosphorus contained therein would prevent silicon atom from moving, as desired, to provide a rough surface. On upper portion
108
b
of the storage node that has a rough surface are deposited a capacitance insulating film and a top electrode for a capacitor (a cell plate) to complete the capacitor. The above described capacitor, with a surface roughened, can have a substantially increased area to satisfy a need for increased capacitance associated with microfabrication.
However, as shown in
FIG. 34
, a silicon seed is also grown from non-doped amorphous silicon adhering to a side surface of a lower portion
105
a
of the storage node. Thus, storage node
107
has a short-circuit margin corresponding to a spacing
110
b
and thus hardly ensured, which facilitates short-circuit between storage nodes. This tendency is more significant as microfabrication further advances, and a reconciliation of providing a rough surface to provide an increased capacitance and ensuring a short-circuit margin between storage nodes is now an issue to be addressed.
SUMMARY OF THE INVENTION
The present invention contemplates a semiconductor device having a rough surface to increase a capacitor in capacitance and simultaneously enhancing a margin preventing short-circuit between capacitors, and a method of manufacturing the same.
In accordance with the present invention the semiconductor device includes: a plug interconnection penetrating an insulating film and connected to an underlying wiring; and a storage node having a lower portion overlying the insulating film and free of a rough surface, and connected to the plug interconnection, and an upper portion overlying the lower portion without covering a side surface of the lower portion, and having the rough surface.
Typically, storage nodes are spaced by an etched trench. As such, the storage node tends to be narrower at a lower portion, which

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