Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-08-03
2003-03-11
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06531357
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof and, more particularly, to a wiring pattern in a region where wiring lines with different pitches are connected, a forming method thereof, and a semiconductor pattern exposure mask used in that method. The present invention is applied to, e.g., a boundary region between a memory cell array region, and a memory cell peripheral circuit region of a semiconductor memory device.
2. Description of the Related Art
It is a common practice to use photolithography in the manufacture of semiconductor devices such as a semiconductor memory, microprocessor, and the like. Photolithography is a technique for irradiating a pattern exposure mask formed with a pattern with light rays, projecting the light rays onto a photoresist on a semiconductor substrate via an optical system to expose the photoresist, and transferring the pattern on the mask onto the semiconductor substrate.
Miniaturization of semiconductor devices is in progress to achieve high integration and low cost. For this purpose, miniaturization of a pattern formed by photolithography must be realized first.
In general, a resolution R and depth of focus DOF in photolithography are expressed by Rayleigh's equations:
R=k
1
(&lgr;/
NA
)
DOF=k
2
(&lgr;/
NA
2
)
where &lgr;: the wavelength of irradiation light, NA: the numerical aperture, and k
1
and K
2
: process constants and the like.
As can be seen from the above equations, it is effective to shorten the wavelength of irradiation light so as to transfer a fine pattern. As a light source of a conventional exposure system, i-line having a wavelength of 365 nm is normally used. In order to form a finer pattern, a KrF excimer laser having a wavelength of 248 nm is currently normally used.
In order to promote further miniaturization, it is required to use a light source of a shorter wavelength, to decrease k
1
and k
2
, and to increase the numerical aperture NA (high NA). As the light source of a short wavelength, an ArF excimer laser having a wavelength of 193 nm is hopeful. However, it is difficult to develop an optical system, photoresist, and the like for the ArF excimer laser, and such system has not reached a practical use yet. Although k
1
and k
2
can be reduced by improving the resist and process, their limit values are around 0.4 to 0.5. Too high an NA is not practical since it is difficult to work a high-NA lens that can cover a large area upon exposure. In addition, a certain depth of focus or more must be assured in actual exposure. However, since the depth of focus drops with increasing NA, as can be seen from the Rayleigh's equations, it is difficult to achieve a high NA in this respect as well.
As described above, improvement of resolution achievable by only improving the wavelength, numerical aperture, and process is limited. Hence, so-called super resolution techniques such as a method using an attenuated phase shifting mask, a method using off-axis illumination upon exposure of a mask pattern, and the like are used as that for further improving resolution. The super resolution technique will be briefly explained below.
In the attenuated phase shifting mask, a translucent film having a transmittance of 3 to 10% is normally formed in place of a chromium film to transmit light so as not to perfectly intercept light even at a line pattern portion, and the phase of transmission light is shifted 180°. At this time, the resolution is improved by forming a steep light intensity distribution at the boundaries between line and space patterns by coherence produced between light transmitted through the line pattern portion and that transmitted through the space pattern portion. By contrast, in a normal mask, a line pattern portion is normally formed of chromium or the like to intercept light so as to prevent the photoresist from being exposed.
In off-axis illumination, an aperture that intercepts light components near the center of a light source is set to irradiate a mask with only obliquely incoming light components. When such off-axis illumination is used, either of ±1st-order diffracted light components are not projected, and the remaining diffracted light component is projected. In this way, the resolution can be improved by the method of forming an image using two luminous fluxes, i.e., 0th-order light and one of ±1st-order diffracted light components.
By contrast, in a normal illumination method, light which is emitted by a light source and with which a mask is irradiated forms an optical image on a semiconductor substrate since three luminous fluxes, i.e., 0th-order light and ±1st-order light components produced by diffraction are projected.
However, the aforementioned super resolution technique is effective to form periodic, dense patterns but can hardly form coarse patterns simultaneously with dense patterns. That is, it is possible to miniaturize patterns on a memory cell array region using the super resolution technique, but it is difficult to form desired patterns on a wiring connection region between the memory cell array region and a peripheral circuit region. In some cases, the patterns of the connection region limit the pitch of a memory cell array, resulting in an increase in chip size of a semiconductor memory.
As described above, in a conventional semiconductor memory, the resolution and depth of focus readily impair due to coherence of light upon forming wiring patterns using photolithography on a boundary region between a memory cell array region where line & space wiring patterns are formed at a very small pitch equal to or lower than the wavelength of a light source of an exposure system, and a peripheral circuit region where wiring patterns are formed at a patch larger than that in the former region. As a result, desired patterns cannot be formed, and disconnection and short-circuiting of wiring patterns readily occur.
It is the first object of the present invention to provide a semiconductor device which can prevent disconnection and short-circuiting of wiring patterns in a region where wiring lines or interconnects with different pitches are to be connected, and can achieve high integration. More specifically, the present invention has as its object to suppress the resolution and depth of focus from impairing upon forming wiring patterns using photolithography in the boundary region between a first region where line & space wiring patterns are formed via very small spaces equal to or smaller than the wavelength of a light source of an exposure system, and a second region where wiring patterns are formed via spaces larger than those of the first region.
It is the second object of the present invention to provide a semiconductor memory device, which can suppress any errors due to dimensional variations at the memory cell array edge portion of a semiconductor memory device and can realize high yield and high reliability, and its manufacturing method.
BRIEF SUMMARY OF THE INVENTION
A semiconductor device according to the first aspect of the present invention, comprises:
a semiconductor substrate;
a first line & space pattern set in which a first, a second, a third, and a fourth line pattern, each of which has a line width L and is made of a conductor, are aligned in turn via a line space S on a first region on the semiconductor substrate;
a second line & space pattern set in which a fifth and a sixth line pattern, each of which has not less than the line width L and is made of a conductor, are aligned in turn via not less than the line space S on a second region on the semiconductor substrate; and
a third line & space pattern set in which a seventh line pattern, which is connected to the first and the fifth line pattern and is made of a conductor, and an eighth line pattern, which is connected to the third line pattern and the sixth line pattern and is made of a conductor, are formed on a third region present between the first and the second region on the semiconductor
Arai Fumitaka
Takeuchi Yuji
Kabushiki Kaisha Toshiba
Le Thao
Nelms David
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