Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-06-29
2002-02-12
Wilczewski, Mary (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S300000, C438S586000, C438S589000, C438S926000, C438S259000
Reexamination Certificate
active
06346438
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a method of manufacturing the same.
Recently, demands have arisen for higher integration degree of LSIs and higher operation speeds thereof. To achieve this purpose, the sizes of respective members constituting a transistor are proportionally reduced. However, a reduction in gate electrode width to about 0.1 &mgr;m poses the following problems.
FIG. 1
is a sectional view schematically showing an example of a conventional MOSFET. In
FIG. 1
, e.g., an SiO
2
gate insulating film
2
, and a gate electrode
3
prepared by heavily doping an n-type impurity such as phosphorus in polysilicon at 2×10
20
cm
−3
or more are sequentially stacked on one major surface of a p-type silicon substrate
1
. An insulating gate sidewall
4
is formed on the side surface of the gate electrode
3
via a thermal oxidized film
10
. An n-type impurity diffusion region
5
called an extension formed to be shallow below the gate sidewall
4
, an n-type impurity diffusion region
6
formed to be deeper than the extension
5
, and a device isolation region
7
made of, e.g., SiO
2
are formed in the surface region of the substrate
1
. And a metal silicide layer
8
is formed on the source/drain region by SALICIDE (Self Align Silicide) method to reduce the resistance value of the source/drain diffusion layers. In the MOSFET shown in
FIG. 1
, the extension
5
and the n-type impurity diffusion region
6
serve as source and drain diffusion layer. The metal silicide layer
8
is also formed on the gate electrode
3
.
In the MOSFET shown in
FIG. 1
, the extension
5
must be controlled to have a high impurity concentration of about 10
19
cm
−3
and a small depth of 0.05 &mgr;m or less in order to suppress increases in short channel effect and electrical resistance value. To make the extension
5
shallow, the ion implantation acceleration voltage must be controlled to be as low as several keV. However, at a low acceleration voltage, the ion current decreases, so ion implantation cannot be complete within an actual processing time.
To prevent the leakage current from increasing by a reverse bias at a p-n junction, the distance must be typically set to 0.07 &mgr;m or more between the bottom surface of the metal silicide layer
8
formed in the surface region of the substrate
1
, and the bottom surface of the n-type impurity diffusion region
6
. The thickness of the metal silicide layer
8
is determined such that the parasitic resistance value of the source/drain diffusion layer becomes much smaller than the resistance value upon continuous application of a voltage to the gate electrode
3
. For this reason, the metal silicide layer
8
must be formed to a predetermined thickness for obtaining lower resistance value, e.g., 0.05 &mgr;m or more. In other words, the n-type impurity diffusion region
6
is formed to position its bottom surface at a depth of 0.12 &mgr;m or more from the surface of the substrate
1
. In this case, however, so-called punch-through may occur to flow a current even upon no application of any voltage to the gate electrode
3
, i.e., in an OFF state.
As a structure for preventing the punch-through, an elevated source/drain structure shown in
FIG. 2B
is known.
FIGS. 2A and 2B
are sectional views, respectively, schematically showing the steps in manufacturing a conventional MOSFET having an elevated source/drain structure. The same reference numerals as in the MOSFET shown in
FIG. 1
denote the same parts in the MOSFET shown in
FIGS. 2A and 2B
, and a description thereof will be omitted.
In manufacturing a conventional MOSFET having an elevated source/drain structure, Si is selectively epitaxially grown on an n-type impurity diffusion region
5
to form an Si film
9
, as shown in FIG.
2
A. That is, a region serving as a source/drain diffusion layer is extended to above a substrate
1
. The Si film
9
is also formed on a gate electrode
3
. As shown in
FIG. 2B
, ions are implanted to form an n-type impurity diffusion region
6
. Further, as described with reference to
FIG. 1
, a metal silicide layer (not shown) is formed to obtain a MOSFET. In
FIGS. 2A and 2B
, the gate electrode
3
is formed to be lower than a gate sidewall
4
in order to prevent electrical connection between the gate electrode
3
and the source/drain region due to the lateral growth of the Si film
9
formed on the gate electrode
3
.
In the MOSFET formed in this manner, although the n-type impurity diffusion region
6
is formed to a satisfactory thickness, its effective depth, i.e., the depth from the surface of the substrate
1
is smaller than that in the MOSFET shown in FIG.
1
. More specifically, according to the MOSFET shown in
FIGS. 2A and 2B
, a larger distance can be set between the bottom surface of the metal silicide layer (not shown) and the bottom surface of the n-type impurity diffusion region
6
. By this method, however, Si grows not only on the n-type impurity diffusion region
5
shown in
FIG. 2A
but also in the lateral direction. As a result, the Si film
9
is also formed on a device isolation region
7
, making it difficult to maintain an insulating state between adjacent transistors.
Although the nMOS has been exemplified, the pMOS also has the same structure as that of the nMOS except for an opposite semiconductor conductivity type. Therefore, the above-described problems also occur in the pMOS.
BRIEF SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device capable of reducing its size and preventing punch-through, and a method of manufacturing the same.
It is another object of the present invention to provide a semiconductor device capable of maintaining an insulating state between devices even upon a reduction in size, and a method of manufacturing the same.
It is still another object of the present invention to provide a semiconductor device capable of reducing its size, preventing punch-through, and maintaining an insulating state between devices, and a method of manufacturing the same.
According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of a) forming, on one major surface of a substrate, a gate structure constituted by either one of a dummy gate electrode and a gate electrode having an insulating film at least on bottom surface, and a device isolation insulating film so as to form a first groove divided by the dummy gate electrode or the gate electrode, to position the dummy gate electrode or the gate electrode in the first groove, and to form the gate structure to have an upper surface level not higher than an upper level of the device isolation insulating film, and b) forming source and drain electrodes in the first groove.
According to the present invention, there is also provided a method of manufacturing a semiconductor device, comprising the steps of forming a dummy gate wiring layer on one major surface of a substrate, forming a semiconductor film on an exposed surface of one major surface of a substrate, forming a semiconductor film on an exposed surface of one major surface of the substrate by using epitaxial growth, and forming, on the semiconductor film, a gate sidewall which is made of an insulator and covers a side surface of the dummy gate wiring layer.
According to the present invention, there is further provided a semiconductor device comprising a substrate, a device isolation insulating film formed on one major surface of the substrate, a gate electrode formed on one major surface of the substrate, a gate wiring layer formed on the device isolation insulating film and connected to the gate electrode, a source electrode and drain electrode arranged on one major surface of the substrate to face each other via the gate electrode, and an insulating film formed on a bottom surface and a side surface of the gate electrode and the gate wiring layer, and wherein the gate electrode, the gate wiring layer, the source electrode, and the drain
Akasaka Yasushi
Matsuo Kouji
Suguro Kyoichi
Tsunashima Yoshitaka
Yagishita Atsushi
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Wilczewski Mary
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