Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-08-23
2002-02-12
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S004000, C438S305000, C438S306000
Reexamination Certificate
active
06346448
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to the manufacture of semiconductor devices, and more particularly to manufacturing semiconductor devices that include lightly-doped diffusion (LDD) regions and self-aligned contact structures on the same substrate.
BACKGROUND OF THE INVENTION
A continuing goal in the manufacture of semiconductor devices is increased density and miniaturization. Such goals can be particularly important in memory devices, such as dynamic random access memories (DRAMs), which may include millions of repeated memory cells. One way to increase device density can be to reduce the space between adjacent structures. For example, in semiconductor devices that include circuit devices, such as insulated gate field effect transistors (IGFETs), it can be desirable to reduce inter-gate spacing.
Reduced inter-gate spacing can present difficulties in forming contacts (including vias). Semiconductor devices can typically include one or more layers that may be connected to one another with contacts. To reduce spacing, and thereby increase density, it can be desirable to place such contacts as close as possible to adjacent structures, such as transistor gates. A preferred method of forming closely spaced contacts is to form self-aligned contacts. Self-aligned contact methods are disclosed in Japanese Patent Application Laid-Open No. Hei 9-134956 and Japanese Patent Application Laid-Open No. Hei 10-144633.
Referring now to
FIG. 2A
, a conventional approach to forming self-aligned contacts may include forming isolation regions
102
and a gate insulator
103
on a semiconductor substrate
101
. Isolation regions
102
and/or a gate insulator
103
may comprise silicon dioxide. A transistor gate layer
104
may then be formed over the semiconductor substrate
101
. A gate layer
104
may comprise polycrystalline and/or amorphous silicon (referred to herein collectively as polysilicon) doped with an impurity. A top insulating layer
105
may then be formed over a transistor gate layer
104
.
A gate pattern (not shown) may then be formed over a top insulating layer
105
that contains a desired gate shape. A gate pattern may comprise a resist, such as photoresist, formed with a patterning process such as a lithography process or the like. Anisotropic etching can then transfer the gate pattern to form a top insulating layer
105
, gate layer
104
and/or gate insulator
103
with a predetermined shape, as shown in FIG.
2
A.
A sidewall insulating film can then be formed over patterned gate structures. A sidewall insulating film may comprise silicon dioxide deposited with chemical vapor deposition (CVD) techniques, for example. An etch back step may then remove the sidewall insulating film to form sidewalls
106
. A top insulating layer
105
and sidewalls
106
can serve to protect a gate layer
104
from subsequent etching steps. In particular, such structures can prevent a gate layer
104
from being exposed when a contact hole is formed in close proximity to a gate layer
104
.
A first and second etch stop layer,
108
and
107
, may then be formed over a substrate. A first etch stop layer
108
may comprise silicon nitride. A second etch stop layer
107
may comprise silicon dioxide. An etch stop layer may prevent a semiconductor substrate
101
from being exposed when a contact hole is formed.
Following the formation of etch stop layers (
108
and
107
), an interlayer insulating film
109
may be formed. An interlayer insulating film
109
may comprise silicon dioxide. A contact hole etch mask
110
may then be formed over the interlayer insulating film
109
. A contact hole etch mask
110
may include openings at the desired location of a contact hole. A conventional semiconductor device following the formation of a contact hole etch mask is shown in
FIG. 2A. A
contact hole etch mask
110
may comprise a layer of patterned resist, or the like.
Referring now to
FIG. 2B
, a conventional method may continue with a first contact hole etch. A first contact hole etch may be an anisotropic etch that is selective to a first etch stop layer
108
. Thus, following a first contact hole etch, a contact hole may be formed through an interlayer insulating film
109
to expose etch stop layer
108
. A conventional semiconductor device following a first contact hole etch is shown in FIG.
2
B.
A second contact hole etch may then occur that is also anisotropic and selective to second etch stop layer
107
. Such an etching can remove a first etch stop layer
108
at the bottom of a contact hole and expose a second etch stop layer
107
. A third contact hole etching may then remove the second etch stop layer
107
at the bottom of a contact hole, thereby exposing a semiconductor substrate
101
at the bottom of a contact hole
113
. A conventional semiconductor device following all contact hole etching steps is shown in FIG.
2
C.
Referring once again to
FIG. 2C
, once a contact hole
113
is formed, the contact hole
113
may be filled with a conducting material. In this way a self-aligned contact may be formed. The contact may be self-aligned, as there is no minimum spacing requirement between a gate layer
104
and a contact due to the protection provided by a sidewall
106
and/or top insulating layer
105
.
In addition to reductions in inter-gate spacing, miniaturization has also resulted in smaller gate lengths for IGFETs. Unfortunately, smaller gate lengths can lead to short channel effects and hot carrier effects, which can adversely affect transistor performance and/or reliability. One way to address such adverse effects can be to form transistors with lightly doped diffusion (LDD) regions (also referred to as lightly doped drains).
A conventional approach to forming LDD regions is disclosed in Japanese Patent Application Laid Open No. Hei 7-202179. The LDD structure is formed in the manufacture of a metal-oxide-semiconductor (MOS) type IGFET.
Referring now to
FIG. 3A
, a conventional method of forming MOS transistors with LDD regions can include forming isolation regions
202
and a gate insulator
203
on a semiconductor substrate
201
. A transistor gate layer
204
may then be formed over the semiconductor substrate
201
. A top insulating layer
205
may then be formed over a transistor gate layer
204
. A gate etch mask (not shown) may then be formed over a top insulating layer
205
. A gate etch mask may include a desired gate shape.
Anisotropic etching can transfer a gate pattern from a gate etch mask to the top insulating layer
205
, gate layer
204
and/or gate insulator
203
to form a predetermined shape, as shown in FIG.
3
A.
Isolation regions
202
and/or a gate insulator
203
may comprise silicon dioxide. A gate layer
204
may comprise polysilicon doped with an impurity. A top insulating layer
205
may comprise silicon dioxide. A gate etch mask may comprise a resist, such as photoresist, formed with a patterning process such as a lithography process, or the like.
Referring now to
FIG. 3B
, a LDD ion implantation step may then be performed. A LDD ion implantation may be a blanket implant at an injection dosage and energy that are relatively small with respect to a subsequent source/drain implant discussed below. In an LDD ion implantation step, a structure formed by top insulating layer
205
, gate layer
204
and gate insulator
203
may serve as an implantation mask. LDD regions are shown as items
207
in FIG.
3
B.
Following a LDD implant step, a sidewall insulating film can then be formed over a semiconductor substrate
201
. A sidewall insulating film may then be etched back to form sidewalls
206
. A sidewall insulating film may comprise CVD silicon dioxide. A conventional semiconductor device following the formation of sidewalls
206
is shown as item FIG.
3
C.
Referring now to
FIG. 3D
, following the formation of sidewalls
206
, a source/drain ion implantation step may be performed. A source/drain ion implantation may be a blanket implant at an injection dosage and energy that are relatively large with respect to the LDD impla
Dang Trung
Walker Darryl G.
LandOfFree
Method of manufacturing a semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing a semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2956781