Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-03-16
2002-06-11
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S229000, C438S301000
Reexamination Certificate
active
06403426
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to a method of manufacturing a semiconductor device comprising a semiconductor body which is provided at a surface with a transistor having a gate insulated from a channel region at the surface of the semiconductor body by a gate dielectric, the gate having an area, by which method an active region of a first conductivity type adjoining the surface is defined in the semiconductor body, and a patterned layer is applied defining the area of the planned gate to be provided at a later stage of the process, after which a dielectric layer is applied, which dielectric layer is provided with a recess at the area of the planned gate by removing the patterned layer, after which impurities are introduced via the recess into the channel region of the semiconductor body in a self-registered way by using the dielectric layer as a mask, and an insulating layer is applied, forming the gate dielectric of the transistor, on which insulating layer a conductive layer is applied thereby filling the recess, which conductive layer is shaped into the gate of the transistor.
A method of manufacturing a semiconductor device of the kind mentioned in the opening paragraph is known from U.S. Pat. No. 5,773,348. In the known method, a stacked pad oxide
itride layer is formed on a surface of the semiconductor body, on which stacked pad oxide
itride layer a patterned photoresist layer is applied, forming the area of the gate planned, hereinafter also called the planned gate area. An oxide layer is selectively deposited on the stacked pad oxide
itride layer, after which the patterned photoresist layer is removed. In a subsequent implantation process, impurities are introduced via the planned gate area into the semiconductor body by using the oxide layer as an ion implantation mask, thereby providing the semiconductor body with an anti-punchthrough impurity region. Then, nitride spacers are formed within the planned gate area at the sidewalls of the oxide layer and the stacked pad oxide
itride layer is removed within the same region. A gate oxide layer is subsequently applied within the planned gate area, followed by the deposition of an amorphous silicon layer filling the planned gate area, which amorphous silicon layer is shaped into the gate of the transistor. Finally, the oxide layer and the underlying stacked pad oxide
itride layer are removed and a salicide process including a two-stage annealing treatment with temperatures as high as 750 to 900° C. is carried out in order to form self-aligned contacts and shallow junction source and drain zones.
Whether impurities are introduced into the semiconductor body by means of diffusion from a chemical source provided at the surface of the semiconductor body or by means of ion implantation, in both cases a high-temperature annealing treatment with temperatures as high as about 900° C. needs to be carried out.
A disadvantage of the known method is that the formation of the gate and the introduction of the impurities via the planned gate area into the semiconductor body take place prior to the formation of the source zone and the drain zone and, hence, prior to the high-temperature two-stage annealing treatment. Because the gate is subjected to the high temperatures of this annealing treatment, serious constraints are imposed on the choice of process compatible materials for the gate. Moreover, the high-temperature anneal will also adversely redistribute the impurities that have been locally introduced into the semiconductor body for punchthrough suppression.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a method of manufacturing a semiconductor device of the kind mentioned in the opening paragraph, which increases the flexibility as regards the implementation of process compatible materials for the gate in a conventional CMOS process flow, and which allows a local introduction of impurities via the planned gate area into the semiconductor body without an adverse redistribution of the introduced impurities at a later stage of the process.
According to the invention, this object is achieved in that the patterned layer consisting of refractory material is applied, which patterned layer acts as a mask during the formation of a source zone and a drain zone of a second conductivity type in the semiconductor body, after which the dielectric layer is applied in a thickness which is sufficiently large to cover the patterned layer, which dielectric layer is removed over part of its thickness by means of a material removing treatment until the patterned layer is exposed, which patterned layer is then removed.
The above-stated measures in accordance with the invention prevent the gate as well as the impurities, which have been locally introduced into the semiconductor body via the recess at the planned gate area, from being exposed to the high temperatures of the annealing treatment associated with the formation of the source zone and the drain zone of the transistor. In this way, the flexibility as regards the use of process compatible materials for the gate is substantially increased, and redistribution of the locally introduced impurities is counteracted.
The planned gate area is defined by depositing a patterned layer, which is composed of refractory material to withstand the high temperatures of the annealing treatment associated with the subsequent formation of the source zone and the drain zone of the transistor. Prior to the removal of the patterned layer, a relatively thick dielectric layer is applied in a thickness which is sufficiently large to cover the patterned layer. The dielectric layer is subsequently removed over part of its thickness by means of, for example, chemical-mechanical polishing until the patterned layer is exposed, which patterned layer is removed by means of selective etching, thereby providing the dielectric layer with a recess at the planned gate area. After the removal of the patterned layer, a dip-etch may be carried out in order to remove a surface layer composed of, for instance, silicon oxide, which may have been advantageously applied to the surface of the semiconductor body in order to protect the semiconductor body against contamination. Impurities are then introduced via the recess into the channel region of the semiconductor body in a self-registered way using the dielectric layer as a mask. Either before or after the introduction of the impurities, an insulating layer is applied, forming the gate dielectric of the transistor. Then, a conductive layer is applied, which fills the recess and is shaped into the gate of the transistor.
The impurities may be introduced into the channel region of the semiconductor body by means of a diffusion process, involving two steps in general. First, the impurities are placed on or near the surface of the semiconductor body by a gaseous deposition step or by coating the surface with a layer containing the desired impurities. This is followed by an annealing treatment in order to further drive-in the impurities into the semiconductor body by means of diffusion. An alternative to the diffusion process is ion implantation. The desired impurities are first ionized and then accelerated by an electric or magnetic field to a high energy level, typically in the range from 1 to 500 keV. A beam of the accelerated high-energy ions strikes the surface of the semiconductor body and penetrates exposed regions thereof. The penetration is typically less than a micrometer below the surface, and considerable damage is done to the crystal lattice during implantation. Consequently, an annealing treatment is required in order to repair the damage the crystal lattice, and to activate the as-implanted impurities.
Due to its ability to more precisely control the number of impurities introduced into the semiconductor body, ion implantation is preferred to diffusion. Moreover, ion implantation allows impurity introduction into the semiconductor body with much less lateral distribution than via diffusion and, hence, allows devices to be manufacture
Montree Andreas H.
Schmitz Jurriaan
Woerlee Pierre H.
Lindsay Jr. Walter L.
Niebling John F.
Waxler Aaron
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