Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-03-16
2002-04-09
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S259000, C438S264000, C438S289000, C438S593000, C438S594000
Reexamination Certificate
active
06368915
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to a method of manufacturing a semiconductor device comprising a semiconductor body which is provided at a surface with a non-volatile memory element having a floating gate situated between an overlapping control gate and a channel region which is situated in the semiconductor body and extends between a source zone and a drain zone, by which method an active region of a first conductivity type adjoining the surface is defined in the semiconductor body, and a floating gate dielectric is provided, to which floating gate dielectric the floating gate is applied, the floating gate having a substantially flat surface portion extending substantially parallel to the surface of the semiconductor body and having sidewall portions extending substantially perpendicularly to the surface of the semiconductor body, which floating gate is provided with an inter-gate dielectric, to which inter-gate dielectric the control gate is applied, which control gate is capacitively coupled to the substantially flat surface portion of the floating gate and to at least the sidewall portions of the floating gate situated adjacent to the source zone and the drain zone.
A method of manufacturing a semiconductor device of the kind described in the opening paragraph is known from U.S. Pat. No. 5,395,778. In the known method, the active region of the semiconductor body is provided with a first insulating layer providing the floating gate dielectric, to which first insulating layer a silicon layer is applied from which the floating gate is formed. After formation of the floating gate, the source zone and the drain zone are provided in the semiconductor body and a second insulating layer is applied providing the inter-gate dielectric. In a next step, a conductive layer is applied from which the overlapping control gate is formed, which overlapping control gate is capacitively coupled not only to the substantially flat surface portion of the floating gate but also to at least the sidewall portions of the floating gate situated adjacent to the source zone and the drain zone.
A disadvantage of the known method is that, at least adjacent to the source zone and the drain zone, the overlapping control gate is insulated from the semiconductor body only by a stack of the first insulating layer providing the floating gate dielectric covered with the second insulating layer providing the inter-gate dielectric. Consequently, parasitic capacitances are induced during operation of the memory element between the overlapping control gate on the one hand and the source zone and the drain zone in the semiconductor body on the other hand, which parasitic capacitances disadvantageously increase the supply voltage of the memory element.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a method of manufacturing a semiconductor device of the kind mentioned in the opening paragraph, which method suppresses the induction of parasitic capacitances between the overlapping control gate and the semiconductor body and, hence, counteracts an increase in the supply voltage of the memory element.
According to the invention, this object is achieved in that after the definition of the active region, a patterned layer is applied, which patterned layer acts as a mask during the formation of the source zone and the drain zone of a second conductivity type in the semiconductor body, after which a dielectric layer is provided in a thickness which is sufficiently large to cover the patterned layer, which dielectric layer is removed over part of its thickness by means of a material removing treatment until the patterned layer is exposed, which patterned layer is removed, thereby forming a recess in the dielectric layer, in which recess a first insulating layer is applied providing the floating gate dielectric of the memory element, to which first insulating layer a first conductive layer is applied filling the recess in the dielectric layer, which first conductive layer is shaped into the floating gate by means of mask etching, which floating gate is covered with a second insulating layer providing the inter-gate dielectric of the memory element, to which second insulating layer a second conductive layer is applied, which second conductive layer is shaped into the overlapping control gate.
The above-stated measures in accordance with the invention enable the manufacture of a non-volatile memory element having a control gate which is capacitively coupled to at least the sidewall portions of the floating gate situated adjacent to the source zone and the drain zone, the overlapping control gate being insulated from the semiconductor body by a stack the thickness of which is increased by a dielectric layer having a thickness which is relatively large compared with the thicknesses of the first insulating layer providing the floating gate dielectric and the second insulating layer providing the inter-gate dielectric of the memory element. In this way, induction of parasitic capacitances between the overlapping control gate and the semiconductor body is suppressed and, hence, an increase in supply voltage is counteracted.
After the definition of the active region, a patterned layer is applied, which is used as a mask during the subsequent formation of a source zone and a drain zone. Prior to removal of the patterned layer, a relatively thick dielectric layer is applied in a thickness which is sufficiently large to cover the patterned layer. The dielectric layer is subsequently removed over part of its thickness by means of, for instance, chemical-mechanical polishing (CMP) until the patterned layer is exposed, which patterned layer is removed by means of selective etching, thereby forming a recess in the dielectric layer. After the removal of the patterned layer, a dip-etch may be carried out in order to remove a surface layer composed of, for instance, silicon oxide, which may have been advantageously applied to the surface of the semiconductor body in order to protect the semiconductor body against contamination. A first insulating layer is applied providing the floating gate of the memory element, to which first insulating layer a first conductive layer is applied filling the recess in the dielectric layer. The first conductive layer is subsequently shaped into the floating gate of the memory element by means of mask etching, the floating gate having a substantially flat surface portion extending substantially parallel to the surface of the semiconductor body and sidewall portions extending substantially perpendicularly to the surface of the semiconductor body. Then, a second insulating layer is applied providing the inter-gate dielectric of the memory element, to which second insulating layer a second conductive layer is applied, which is shaped into the overlapping control gate of the memory element by means of mask etching. The overlapping control gate is capacitively coupled not only to the substantially flat surface portion of the floating gate but also to at least the sidewall portions of the floating gate situated adjacent to the source zone and the drain zone. An additional removal of the second insulating layer and the first insulating layer using the same mask as applied during etching of the control gate is not required, but may be beneficial in case a material with a high dielectric constant is applied for the second insulating layer and/or the first insulating layer.
In order to achieve a large capacitive coupling between the floating gate and the overlapping control gate, it is advantageous to use an oversized mask during etching of the first conductive layer into the floating gate. In that way, the conductive material of the floating gate will stretch out over the dielectric layer, which is coated with the first insulating layer, to substantially beyond the recess in the dielectric layer at least in the directions of the source zone and the drain zone.
For MOS devices with channel lengths decreasing below about 2 &mgr;m, short-channel effects start to play an important rol
Montree Andreas H.
Schmitz Jurriaan
Woerlee Pierre H.
LandOfFree
Method of manufacturing a semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing a semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2819203