Method of manufacturing a semiconductor device

Details Method of manufacturing a semiconductor device Method of manufacturing a semiconductor device

1999-10-04

2001-10-16

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S239000, C438S251000, C438S256000, C438S393000, C438S394000, C438S399000, C438S586000, C438S595000, C438S657000, C438S682000

Reexamination Certificate

active

06303432

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device including a plurality of field-effect elements of different structures, and more particularly, to a method of manufacturing a semiconductor device including field-effect elements whose gate electrodes comprise metal silicide.
2. Description of the Background Art
Progress in design and processing techniques has enabled fabrication of a sophisticated integrated circuit, wherein a plurality of integrated circuits, which conventionally would be fabricated through different processes, are mounted on a single chip. In this way, an attempt is made to impart improved functions to the integrated circuit and to increase the operating speed of the integrated circuit by assembling the integrated circuits into a single chip. Among integrated circuits having such a structure, an integrated circuit wherein a sophisticated integrated logic circuit (hereinafter referred to as a “logic circuit”) such as a micro-processing unit (MPU) and a DRAM (Dynamic Random Access Memory) are formed into a single chip is called a hybrid DRAM. In order to fabricate an integrated circuit like hybrid DRAM, MOS-type field-effect elements having different structures according to the purpose thereof must be assembled into a single chip of the integrated circuit.
In conventional processes through which DRAM and a logic circuit have been fabricated separately, in order to reduce a delay in a logic circuit, metal silicide is formed on the surface of the gate electrode or a source/drain region according to the salicide (self-aligned silicide) technique, thus reducing the resistance of the logic circuit. In DRAM, slight deterioration of the junction characteristics of the source/drain region accounts for volatilization of data stored in a capacitor. For this reason, metal silicide, which would deteriorate the junction characteristics of the source/drain region, is not formed in the source/drain region. Low-resistance material having a polycide structure, which is a multilayered structure comprising polysilicon and a metal silicide film, is used for a gate electrode, thus reducing a delay in the gate electrode.
Since the process for forming the gate electrode of the logic circuit differs from the process for forming the gate electrode of the DRAM, these processes cannot be applied directly to integration of the logic circuit and the DRAM into a single chip. Thus, metal silicide has been formed even on the surface of the gate electrode of a DRAM memory cell by the salicide technique. Accordingly, the surface of the gate electrode of the DRAM memory cell, the surface of the gate electrode of the logic circuit, and the surface of the source/drain region of the logic circuit are provided with a metal silicide layer, thereby reducing a delay in the logic circuit and the DRAM memory cell. Since the metal silicide layer is not formed on the surface of the source/drain region of the DRAM memory cell, a leakage current developing in a pn junction is prevented, thus improving the reliability of the DRAM memory cell.
A method of manufacturing a conventional semiconductor device will now be described by reference to
FIGS. 17 through 19
.
FIGS. 17 through 19
are cross-sectional views showing a process of manufacturing a conventional semiconductor device. In
FIG. 17
, reference numeral
101
designates a semiconductor substrate;
102
designates an isolation oxide film such as a silicon oxide film;
105
designates a gate oxide film;
106
designates a polysilicon layer; and
1061
designates a silicon nitride film.
First, after formation of the isolation oxide film
102
in an isolation region of the semiconductor substrate
101
, the gate oxide film
105
, the polysilicon layer
106
, and the silicon nitride film
1061
are formed, in this sequence, over the entire surface of the semiconductor substrate
101
. The semiconductor substrate
101
is etched while a mask (not shown) is placed on gate electrode formation regions, whereby the silicon nitride film
1061
is left in only the gate electrode formation regions. The polysilicon layer
106
is etched while the silicon nitride film
1061
is used as a mask.
FIG. 17
is a cross-sectional view showing the semiconductor device after completion of these manufacturing steps. The silicon nitride film
1061
is then eliminated (not shown).
In
FIG. 18
, reference numeral
108
designates a side wall; and
1010
through
1015
designate source/drain regions. First, impurities are implanted into the semiconductor substrate
101
through ion implantation, thus forming the source/drain regions
1010
through
1013
. A silicon oxide film (not shown) is deposited on the entire surface of the semiconductor substrate
101
through chemical vapor deposition (CVD), and the entirety of the logic circuit is etched back, to thereby form the side walls
108
. Subsequently, ions are implanted into the semiconductor substrate
101
, so that the source/drain regions
1014
and
1015
are formed. At the time of etchback of the semiconductor substrate
101
for the purpose of forming the side walls
108
, the gate oxide film
105
is left on the surfaces of the source/drain regions
1010
to
1013
.
FIG. 18
is a cross-sectional view showing the semiconductor device after completion of the foregoing manufacturing step.
The gate oxide film
105
is selectively eliminated from the surfaces of the source/drain regions
1014
and
1015
within the logic circuit region (not shown).
In
FIG. 19
, reference numeral
1071
designates a metal layer; for example a tungsten (W) layer; and
107
designates a metal silicide layer. As shown in the drawing, after formation of a metal (e.g., tungsten) layer
1071
on the entire surface of the semiconductor substrate
101
by means of sputtering, the semiconductor substrate
101
is subjected to heat treatment in a nitrogen atmosphere. The metal silicide layer
107
is formed over the surfaces of the polysilicon layer
106
and the source/drain regions
1014
and
1015
by the salicide technique.
FIG. 19
is a cross-sectional view showing the semiconductor device after completion of the foregoing manufacturing step. As is evident from
FIG. 19
, since the surfaces of the source/drain regions
1010
and
1011
of the DRAM memory cell are covered with the gate oxide film
105
, the metal silicide layer
107
is not formed on the surfaces of the source/drain regions
1010
and
1011
. Subsequently, the metal layer
1071
which in not utilized for forming the metal silicide layer
107
is eliminated through use of an aqueous ammonium solution (not shown). Capacitors and wiring layers are formed in the semiconductor substrate
101
, whereby a conventional semiconductor device is completed (not shown).
Japanese Patent Application Laid-Open No. Hei-1-264257 describes a method of manufacturing a semiconductor device, in which a metal silicide layer is formed on the surfaces of gate electrodes of DRAM memory cells and surrounding circuits as well as on the surfaces of the source/drain regions of the surrounding circuits.
However, in association with progress in miniaturization of semiconductor device, the thickness of the gate oxide film
105
becomes thinner. As a result, the gate oxide film
105
, which is exposed during the etchback phase for forming the side walls
108
, is also etched, thus in turn exposing the surfaces of the source/drain regions
1010
and
1011
. The metal silicide layer
107
is disadvantageously formed on the surfaces of the source/drain regions
1010
and
1011
of the DRAM memory cells, as is the case in the logic circuit. In the event that a metal silicide layer is formed on the sources of the source/drain region of a DRAM memory cell, the junction characteristics of the source/drain region will be deteriorated, thereby causing volatilization of the data stored in a capacitor and considerably degrading reliability of the DRAM memory cell.
Even if the side walls
108
can be formed with the gate oxide film
105

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