Method of manufacturing a semiconductor device

Details Method of manufacturing a semiconductor device Method of manufacturing a semiconductor device

1999-06-04

2001-06-19

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S217000, C438S228000

Reexamination Certificate

active

06248619

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device by which a device having a reliable triple well structure can be manufactured by independently adjusting electrical characteristic of respective MOSFETs without an additional mask process, when performing ion implantation process for adjusting the threshold voltage of a transistor which will be formed on a peripheral circuit region and for adjusting the threshold voltage of a transistor which will be formed on a cell region.
2. Description of the Prior Art
A device having the triple well structure has an advantage that MOSFETs having independently different substrate bias from each other can be manufactured by differentiating the well concentration of a P-well, an isolated P-well (R-well) etc. However, in order for the device to have these electrical characteristic of MOSFETs, it additionally requires a process of forming wells corresponding to the respective MOSFET characteristics and a process of controlling a threshold voltage (hereinafter called Vt) to obtain the threshold voltage Vt.
In forming a conventional triple well, ions are implanted into the cell regions and the peripheral circuit regions, on which a NMOS will be formed, so as to adjust the threshold voltage Vt thereof after the N-channel Vt mask process. Then, more than a two-step photolithography process and an ion implantation process are performed to adjust the threshold voltage Vt in the cell region on which the NMOS will be formed, as well as that in the peripheral circuit regions on which a PMOS will be formed, after the P-channel Vt mask process. Also, if respective threshold voltages Vt are adjusted using these processes, the threshold voltages Vt in the peripheral circuit regions on which both the PMOS and NMOS will be formed and in the cell region on which the NMOS will be formed, are organically varied to each other during respective ion implantation process. In other words, the ion implantation process for adjusting the threshold voltage Vt in the peripheral circuit regions on which the NMOS will be formed, will affect the threshold voltage Vt in the cell region on which the NMOS will be formed, while the ion implantation process for adjusting the threshold voltage Vt in the peripheral circuit regions on which the PMOS will be formed, will affect the threshold voltage Vt in the cell region on which the NMOS will be formed, thereby making it difficult to independently adjust the threshold voltages of respective MOSFETs. Thus, the conventional method has a disadvantage that it necessarily requires separate photolithography process. As a result, a low production rate is resulting since it requires an additional mask process.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method of manufacturing a semiconductor device by which electrical characteristic of respective MOSFETs are independently adjusted to form a device having a reliable triple well structure without an additional mask process, when performing an ion implantation process for adjusting the threshold voltage in a transistor to be formed on the peripheral regions and in a transistor to be formed on a cell region.
In order to accomplish the above object, the method of manufacturing a semiconductor device comprises the steps of establishing, in a semiconductor device, a cell region in which an NMOS will be formed and a peripheral circuit region in which NMOS and PMOS will be formed and then forming a sacrifice oxide film and an ion barrier oxide film on the entire structure; performing ion injection process on the cell region in which the NMOS will be formed and the peripheral circuit region in which the PMOS will be formed, thereby to form a low concentration impurity injection region; sequentially removing said ion barrier oxide film formed on the cell region in which the NMOS will be formed and the peripheral circuit region in which the PMOS will be formed, performing ion injection process on selected regions of the cell region in which the low concentration impurity injection region is formed and the NMOS will be formed and on the peripheral circuit region in which the PMOS will be formed and injecting threshold voltage adjust ions into them; performing ion injection process on said low concentration impurity regions of the cell region in which the NMOS will be formed and on the peripheral circuit region in which the NMOS will be formed, thereby to form a R-well region and a P-well region, respectively; and removing said ion barrier oxide film on the peripheral circuit region in which the NMOS will be formed and then performing the threshold voltage adjust ion injection process on the cell region in which the NMOS will be formed and the peripheral circuit region in which the NMOS will be formed.


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