Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-05-03
2001-01-16
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S257000, C438S258000, C438S307000, C438S529000
Reexamination Certificate
active
06174759
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to a method of manufacturing a semiconductor device, in which a semiconductor body is provided at a surface with a low-voltage field effect transistor and with a non-volatile memory cell in the form of a field effect transistor with a floating gate, in which method the surface is provided with a dielectric layer on which a first polycrystalline or amorphous silicon layer (further referred to as poly) is deposited which is patterned at the location of the memory cell to be formed, whereafter a first doping step is performed for forming source and drain zones of the memory cell, while, during said doping step, the region where the low-voltage transistor is formed is masked against doping by the poly layer, and in a subsequent series of steps the poly layer is patterned at the area of the low-voltage transistor, and source and drain zones of the low-voltage transistor are formed by means of a second doping step. Such a method is known from, inter alia U.S. Pat. No. 5,395,778.
For special uses, for example for microcontrollers or for chip cards, integrated circuits are nowadays required in which logic intended for the conventional data processing is combined with non-volatile memory space for the purpose of data storage. For the logic, use is preferably made of a standard CMOS process with which transistors having optimum properties can be obtained. Generally, these transistors are designed for operation at a relatively low voltage, i.e. at a voltage of less than, for example 5 V. The memory consists of memory cells each comprising a transistor with a floating gate. Usually, a control gate, which is electrically separated from the floating gate by means of an intermediate insulating layer, is arranged above this floating gate. Written information is represented by the charge state of the floating gate which determines the threshold voltage of the transistor. The information can be read by determining the conduction of current through the transistor at a given voltage across the control gate.
Said U.S. Pat. No. 5,395,778 describes a method in which, with a minimal number of extra process steps, a CMOS circuit made in a standard CMOS process is combined with a non-volatile memory in a common silicon body. Since the manufacture of such a non-volatile memory is not compatible with a standard CMOS process, said U.S. Pat. No. 5,395,778 proposes a method in which first a series of essential steps is performed for manufacturing the memory, such as the definition of the floating gate from a polycrystalline silicon layer (poly silicon), a doping step for the source/drain and an oxidation step for oxidizing the side walls of the floating gate. During these steps, the active regions of the semiconductor body where the logic is provided are entirely masked by the poly layer. When the essential steps of providing the memory have been performed, the process can be continued with the standard CMOS process for the logic.
In certain types of non-volatile memories, it is desirable to use voltages which are higher than 5 V, for example a voltage of 9-20 V. This situation occurs, for example in memories of the EEPROM type in which use is made of the Fowler-Nordheim tunnel mechanism during writing and/or erasing. To supply such relatively high voltages, the peripheral electronics of the memory require transistors which can cope with these high voltages and must therefore have a breakdown voltage of approximately 14 V. In addition to these transistors, here referred to as high-voltage transistors, each cell in an EEPROM is usually provided with an access transistor which isolates the memory cell electrically from other memory cells and connects the floating gate transistor to a bit line, and which should also be able to cope with said high voltage. This transistor is usually of the same conductivity type as the memory transistor.
SUMMARY OF THE INVENTION
It is, inter alia, an object of the invention to provide a method of the type described in the opening paragraph, in which a non-volatile memory can be combined with a standard CMOS process, and in which also high-voltage transistors can be realized without any noticeable deterioration of quality of the low-voltage transistors of the CMOS logic. It is a further object of the invention to realize these high-voltage transistors in a minimal number of extra process steps.
According to the invention, a method of the type described in the opening paragraph is characterized in that the semiconductor body is also provided with a high-voltage field effect transistor having a gate which is patterned simultaneously with the floating gate of the memory cell, while, during the first doping step, the semiconductor body is doped also at the area of the source and drain zones of the high-voltage transistor, whereafter edges of the gate of this transistor are provided with spacers and, during the subsequent, second doping step, higher doped parts are formed in non-masked parts of the source and drain zones of the high-voltage transistor. Since the first doping step is independent of the CMOS transistors, this step may be performed in such a way, for example as regards concentration and/or implantation energy, that a favorable breakdown voltage is obtained in the high-voltage transistor. Since the source/drain doping step for the high-voltage transistor can be performed simultaneously with the source/drain doping in the memory cell, it is possible to limit the number of process steps. Since the logic region is covered with poly, it is possible to cover the walls of the floating gate and the gate of the high-voltage transistor with an oxide layer by means of an oxidation step which is optimized for this part of the process, inter alia, in connection with the breakdown voltage, without affecting the logic properties.
A preferred embodiment of a method according to the invention is characterized in that the dielectric layer is provided in the form of a silicon oxide layer having a larger thickness at the area of the high-voltage transistor than at the area of the low-voltage transistor. In most embodiments, the gate oxide of the high-voltage transistor can be formed simultaneously with the gate oxide of the floating gate transistor.
The non-volatile memory may be implemented, for example, as an EPROM, or as a Flash EPROM, etc. Particular advantages are obtained in the case where the memory is of the EEPROM type as described hereinbefore. An important embodiment of a method according to the invention is therefore characterized in that, prior to depositing the poly silicon layer, the silicon oxide layer is locally provided with a tunnel oxide at the location of the memory cell, where the oxide is so thin that charge carriers can move by means of the tunnel effect between the floating gate and the semiconductor body during writing and/or erasing data. A preferred embodiment of such a method, by which the number of process steps can be limited, is characterized in that, simultaneously with the formation of the tunnel oxide, the low-voltage transistor is provided with gate oxide having a thickness which is equal or at least substantially equal to the thickness of the tunnel oxide.
When such a cell is written or erased, a high voltage is usually applied to the drain of the memory transistor. An important embodiment is characterized in that the high-voltage transistor and said low-voltage transistor are provided as transistors of the same conductivity type as the transistor with the floating gate, the high-voltage transistor constituting a selection or access transistor of the memory cell. High-voltage transistors of the same conductivity type in the peripheral electronics of the EEPROM are simultaneously manufactured with the access transistors in the memory cells. An important preferred embodiment of a device according to the invention is therefore characterized in that at least a further high-voltage transistor and at least a further low-voltage transistor of the opposite, complementary, conductivity type are provided, with ga
Dormans Guido J. M.
Garbe Joachim C. H.
Verhaar Robertus D. J.
Biren Steven R.
Niebling John F.
Pompey Ron
U.S. Philips Corporation
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