Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
1998-10-07
2001-09-18
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S758000, C438S933000
Reexamination Certificate
active
06291352
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to a method of manufacturing a semiconductor device with a semiconductor body, by which method a polycrystalline or amorphous semiconductor layer is provided over the entire device in a stage in which the device has been provided with a metallization layer. Such methods are generally known, inter alia for the manufacture of integrated circuits. The stage of the process in which the wiring, for example in the form of aluminum tracks, is provided is called the back end of the process. It is no longer possible to carry out process steps at high temperatures in this stage, i.e. at temperatures higher than 500° C., on account of the presence of the aluminum. This temperature limitation has the disadvantage that certain process steps are no longer possible in this stage, steps which can indeed be carried out advantageously in an earlier stage and which would also offer important advantages in the back end of the process. Among the process steps belonging to this category are the CVD (or LPCVD) deposition of polycrystalline (or amorphous) silicon. Amorphous or polycrystalline silicon layers may be used in the metallization stage of IC processes as antireflex coatings or as etching stoppers for etching back of tungsten layers or as dielectric layers in metal-metal antifuses in programmable arrays. The deposition temperature, however, is usually higher than 550° C., which is not compatible with standard aluminum metallizations. Polycrystalline or amorphous silicon is accordingly often deposited in an alternative manner at a lower temperature, for example by means of plasma CVD or by sputtering. These processes often result in a lesser material quality, inter alia owing to impurities and/or a less good step covering. In addition, these processes are usually single-wafer processes, in contrast to CVD which takes place in batches and accordingly as a much shorter process time.
SUMMARY OF THE INVENTION
The invention has for its object inter alia to render it possible to use silicon-containing layers formed by means of CVD also in the back end of standard IC processes.
According to the invention, a method of the kind described in the opening paragraph is for this purpose characterized in that the semiconductor layer is provided as a Ge
x
Si
1−x
layer, referred to as GeSi layer for short hereinafter, by means of CVD at a temperature which is lower than 550° C., and preferably lower than 500° C., x representing the molar fraction of Ge. The presence of Ge as opposed to pure Si renders it possible to lower the deposition temperature considerably, i.e. to a temperature below 500° C., so that it is possible to provide polycrystalline or amorphous silicon layers by means of CVD in the presence of Al or some other metal layer which melts or reacts chemically at a comparatively low temperature.
An important embodiment in which the advantages of a polycrystalline or amorphous GeSi layer are obtained in photolithographical process steps is characterized in that a photoresist layer is provided over the device after the GeSi layer and is patterned through exposure and development. An embodiment frequently occurring in the manufacture of integrated circuits is characterized in that the GeSi layer is provided on a dielectric layer, and in that the pattern formed in the photoresist layer is transferred into the GeSi layer and the subjacent dielectric layer by means of etching. If the GeSi layer is mainly used as an antireflex layer here, the pattern may advantageously be transferred into the GeSi layer and subsequently, with the photoresist layer being present, into the subjacent dielectric layer, whereupon the photoresist layer is removed. A preferred embodiment, in which the advantages of the use of a hard mask are obtained owing to the GeSi layer, is characterized in that, after the pattern has been transferred into the GeSi layer, the photoresist layer is removed before the dielectric layer is subjected to the etching treatment.
An important field of application of the invention is the field of providing the interconnections in integrated circuits where, after etching, a second metal layer is provided over the surface thus obtained, filling up entirely the openings in the dielectric layer formed by etching, from which second metal layer a pattern corresponding to the pattern in the dielectric layer is subsequently formed by means of a homogeneous removal of metal. The metal layer may be advantageously etched back by means of chemical-mechanical polishing. A preferred embodiment, which has the advantage inter alia that metal remnants and/or other impurities are also removed, is characterized in that the material-removing step is stopped when the GeSi layer is reached, whereupon the GeSi layer is removed by means of an etching treatment.
The use of undoped amorphous silicon layers as antifuses is known, which layers can be brought from a non-conducting state into a conducting state through the application of a sufficiently strong electric field. A further embodiment of a method according to the invention, which may be used inter alia in the manufacture of programmable non-volatile memories or, for example, so-called FPGAs (field programmable gate arrays), is characterized in that the GeSi layer is provided in the form of an amorphous layer between two metal conductors so as to form an electrically programmable element which can be brought from a high-ohmic state into a low-ohmic state through the application of a voltage between the metal conductors.
REFERENCES:
patent: 4435445 (1984-03-01), Alfred et al.
patent: 5091767 (1992-02-01), Bean et al.
patent: 5604157 (1997-02-01), Dai et al.
patent: 5702963 (1997-12-01), Vu et al.
patent: 09260293A (1997-03-01), None
Juffermans Casparus A. H.
Montree Andreas H.
Woerlee Pierre H.
Biren Steven R.
Chen Kim-Chan
U.S. Philips Corporation
Utech Benjamin L.
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