Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-05-30
2002-11-12
Lee, Eddie (Department: 2815)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S290000, C438S291000, C438S303000, C438S305000, C257S285000, C257S657000, C257S917000
Reexamination Certificate
active
06479356
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same. More particularly, the invention relates to a semiconductor device structured to make MIS transistors therein smaller than before, and to a method for manufacturing the semiconductor device thus structured.
2. Description of the Background Art
There exists a known scaling rule that defines rules for designing MIS (metal insulator semiconductor) transistors. The MIS transistor has a gate insulating film constituted illustratively by an oxide film. On both sides of the gate insulating film are an electrode made of a metal and a gate region composed of a semiconductor. Impurities of a predetermined density are diffused throughout the semiconductor making up the gate region. According to the scaling rule above, if the gate length of the transistor is 1/K, then the density of impurities to be diffused in the gate region must be multiplied by a factor of K.
FIG. 18
is a cross-sectional view of a former single drain type transistor
10
. The transistor
10
has a substrate
12
including a channel injection region
14
. Formed near the surface of the channel injection region
14
are a first and a second source drain region
16
and
18
. In a region interposed between the first and the second source drain region
16
and
18
, the channel injection region
14
is covered with an insulating film
20
. On top of the insulating film
20
is provided with a gate electrode
22
.
If the former transistor
10
is illustratively an N channel transistor, then the channel injection region
14
must be a P-type semiconductor as well as the first and the second source drain region
16
and
18
must be an N-type semiconductor. The structure above is implemented by implanting impurities such as phosphorus (P) (called N-type impurities hereunder) into the channel injection region
14
and into the two source drain regions
16
and
18
, and by implanting impurities such as boron (B) (called P-type impurities hereunder) also into the first and the second source drain region
16
and
18
. The N-type impurities should have a concentration high enough to overcome the P-type impurities when implanted into the first and the second source drain region
16
and
18
.
The former transistor
10
may be made smaller in size when the concentration of impurities in the channel injection region
14
is increased. However, higher impurity concentrations in the channel injection region
14
tend to increase the probability of carriers such as electrons and holes colliding with impurities in the same region
14
. The greater the probability of carriers colliding with impurities in the channel injection region
14
, the lower the operating speed of the transistor
10
. It follows that as the former transistors
10
are made smaller in size, it becomes increasingly more difficult to maintain their high-speed performance.
Where the concentration of impurities is to be boosted in the channel injection region
14
of the former transistor
10
, the impurity concentration in the first and the second-source drain region
16
and
18
thereof must also be increased. This means that as transistors
10
are getting smaller, impurities are more likely to be highly concentrated near PN junctions formed at boundaries between the first or second source drain region
16
or
18
on the one hand and the channel injection region
14
on the other hand.
The breakdown strength of the PN junction decreases as the impurity concentration nearby increases. The capacitance of the PN junction is greater the higher the impurity concentration nearby. For these reasons, it is difficult for former transistors
10
to be made increasingly smaller in size while maintaining their high junction breakdown strength and their low junction capacitance.
Furthermore, the intensity of an electric field generated in the PN junction is greater the higher the concentration of impurities nearby. The higher the field intensity levels of the PN junction, the more likely hot carriers to be appeared inside the transistor
10
. As a result, former transistors
10
tend to be less stable in their operation the smaller they are in size. Miniaturization of former single drain type transistors
10
thus involves these and other related problems.
FIG. 19
is a cross-sectional view of another former transistor
24
. The structure of the transistor
24
is a known one proposed to solve operation speed-related problems of the single drain type transistor
10
. The transistor
24
has a gate region
26
near the surface of a substrate
12
. The gate region
26
comprises a first and a second high-concentration channel injection region
28
and
30
, as well as a low-concentration channel injection region
32
. The first and the second high-concentration channel injection region
28
and
30
are formed near boundaries with the first and the second source drain region
16
and
18
respectively. The low-concentration channel injection region
32
is interposed between the first and the second high-concentration channel injection region
28
and
30
.
FIG. 20
is a graphic representation showing impurity concentration levels in the transistor
24
which is taken along line XO-XXO in FIG.
19
. Into the substrate
12
and gate region
26
of the transistor
24
, impurities of the same type (e.g., P-type impurities such as boron (B)) are implanted. Into the first and the second source drain region
16
and
18
, impurities opposite in type to those contained in the substrate
12
and gate region
26
(e.g., N-type impurities such as phosphorus (P)) are implanted. In
FIG. 20
, a broken line with reference character “Sub” indicates a level of the concentration of impurities in the substrate
12
. Reference characters CD, C/D and S/D represent levels of P- or N-type impurities distributed in the low-concentration channel injection region
32
, in the first and second high-concentration channel injection region
28
and
30
, or in the first and the second source drain region
16
and
18
, respectively.
In the former transistor
24
, as shown in
FIG. 20
, the impurity concentration (CD) of the low-concentration channel injection region
32
is set to be slightly higher than the impurity concentration (Sub) of the substrate
12
. The impurity concentration (C/D) of the first and the second high-concentration channel region
28
and
30
is established so as to be higher than the impurity concentration (S/D) of the first and the second source drain region
16
and
18
in the transistor
28
.
In the transistor
24
, PN junctions are formed at boundaries between the first and the second source drain region
16
and
18
on the one hand and the first and the second high concentration channel region
28
and
30
on the other hand. As a result, depletion layers are formed near these boundaries.
Such depletion layers can expand in keeping with fluctuations of a voltage applied to the transistor
24
. A depletion layer on the low impurity concentration side tends to be more expansive than a depletion layer on the high impurity concentration side.
For that reason, if the impurity concentration of the first and the second high-concentration channel region
28
and
30
is set to be lower than the impurity concentration of the first and the second source drain region
16
and
18
in the transistor
24
, i.e., in the case of a setting opposite to that described earlier (this setting is called the comparative setting hereunder), depletion layers expand mainly on the side of the first and the second high-concentration channel region
28
and
30
. In this case, the gate length is reduced in inverse proportion to the depletion layers being expanded. The operation threshold value of transistors varies with changes in their gate length. Thus the comparative setting above makes it difficult to maintain a stable operation threshold value especially when the transistor
24
is small in size.
In the setting of
FIG. 20
, by contrast, the depl
Diaz José R.
Lee Eddie
McDermott & Will & Emery
Mitsubishi Denki Kabushi Kaisha
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