Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having schottky gate
Reexamination Certificate
2001-12-26
2003-04-01
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having schottky gate
C438S181000, C438S526000, C438S533000, C438S571000, C438S582000
Reexamination Certificate
active
06541319
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to a method of manufacturing a self-aligned gate transistor, and more particularly to, a method of forming an improved channel structure.
2. Description of the Prior Art
Generally, in order to manufacture a transistor having a good direct current (DC) and radio frequency (RF) characteristic, it is inevitably required that the length of a gate, the depth of a channel, the resistance between a source and a gate, and between a gate and a drain, etc. be reduced, As the length of the gate is reduced, however, a short channel effect is further severe along with increase in the resistance of the gate. An increase in the resistance of the gate degrades a gain or a noise characteristic of the device. In order to prevent this, a gate, a lower side of which is small but an upper side of which is great, so called a gate having a T-type shape was proposed. An increase in the short channel effect causes to lower a breakdown voltage between the source and drain to degrade the power characteristic. In order to prevent this, a method has been used by which a P-type impurity is implanted below a current transfer channel to obviate a trail of a N-type impurity. However, the parasitic capacitance is increased due to implantation of the P-type impurity, which degrades an alternating current (AC) characteristic such as f
T
(cut-off frequency) or f
max
(maximum oscillation frequency) of the device. Therefore, there usually exists a trade-off to design P-type and N-type channels for optimizing DC and RF characteristics.
Of these methods, a method by which P-type impurity ions having different concentration are implanted below the channel layer and below the source and drain for form a channel, has disadvantages that the process is complicated since two step lithography processes are required for P-type ion implantation process having different concentration and irregularity in the shape and characteristic is caused due to mismatching of alignment.
Another method is one so called a pocket type ion implantation method by which P-type impurity ions are not implanted below the channel layer but P-type impurity ions are implanted only below the source and drain. This method, however, has a problem that the resistance between the source and the gate, and between the gate and the drain is increased.
SUMMARY OF THE INVENTION
The present invention is contrived to solve the above problems and an object of the present invention is to provide a method of forming an improved transistor having a channel structure useful in manufacturing a self-aligned transistor having a good DC and RF characteristic.
Also, another object of the present invention is to improve noise and high frequency characteristics by reducing the resistance between a source-gate and a gate-drain while reducing a short channel effect and to increase the power density of a power device by increasing the current density between source and drain.
In order to accomplish the above object, a method of manufacturing a self-aligned gate transistor according to the present invention, is characterized in that it comprise the steps of implanting P-type impurity ions only below a channel region below a gate and below a source and drain electrode; and depositing a refractory gate metal having a good high temperature stability to form a gate pattern using a dry etch method.
Also, preferably, a method of manufacturing a self-aligned gate transistor according to the present invention further comprises a first step of etching the gate pattern including depositing the gate without implanting P-type impurity ions into a narrow region between the source-gate and the gate-drain and depositing; a second step of implanting ions using the gate as a mask to form a LDD (lightly doped drain) layer; a third step of performing N+ type ions on the source/drain region; a fourth step of forming a resistant metal for ohmic contact and performing an annealing process to form an ohmic contact layer; and a fifth step of forming a source/drain electrode for contact to the ohmic contact layer.
According to a preferred embodiment of the present invention, P-type impurity ions are implanted only below the underlying gate channel region and the source and drain electrode and a refractory gate metal having a good high-temperature stability. Then, a gate pattern is formed by a dry etch method. Next, LDD (lightly doped drain) ion implantation and N+ ion implantation are performed in order to reduce the resistance between the source-gate and the gate-drain using the gate pattern. Next, a refractory gate metal having a good high-temperature stability is activated so that a transistor having a self aligned gate having a good DC and RF characteristic and a good high-temperature stability.
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M. Nagaoka, et al., “Refractory Wn/W Self-Aligned Gate GaAs Power metal Semiconductor Field Effect Transistor for 1.9-GHz Digital Mobile Communication System Operating with a single Low-Voltage Power Supply,” Jpn. J. Appl. Phys. vol. 33, pp. 767-770, Jan. 1994.
K. Nishihori, “A Self-Aligned Gate GaAs, MESFET with P-Pocket Layers for High-Efficiency Linear Power Amplifiers,” IEEE Transactions on Electron Devices, vol. 45, pp. 1385-1392, Jul. 1998.
Kim Hea Cheon
Lim Jong Won
Mun Jae Kyoung
Blakely & Sokoloff, Taylor & Zafman
Electronics & Telecommunications Research Institute
Jr. Carl Whitehead
Smoot Stephen W.
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