Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
1999-08-03
2001-04-10
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S126000, C438S127000
Reexamination Certificate
active
06214640
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a method of packaging a semiconductor chip or an array of such semiconductor chips.
BACKGROUND OF THE INVENTION
In the constriction of semiconductor chip package assemblies, it has been found desirable to interpose encapsulating material between and/or around elements of the semiconductor packages in an effort to reduce and/or redistribute the strain and stress on the connections between the semiconductor chip and a supporting circuitized substrate during operation of the chip, and to seal the elements against corrosion, as well as to insure intimate contact between the encapsulant, the semiconductor die and the other elements of the chip package.
It is often desirable to package a semiconductor chip assembly such that it can be handled with less fear of damage to the assembly so that a heat sink can be married with the semiconductor chip. However, if a semiconductor chip assembly is to be so packaged, the utmost care must be taken during the packaging process to avoid affecting the integrity of the terminals on the chip carrier. In particular, it is important to avoid contaminating the terminals on the chip carrier with the encapsulant.
Certain designs have reduced solder connection fatigue by redistributing the thermal cycling stress into a portion of the chip package itself. An example of such a design is shown in U.S. Pat. Nos. 5,148,265 and 5,148,266, the disclosures of which are incorporated herein by reference. One disclosed embodiment of these patents shows the use of a chip carrier in combination with a compliant layer to reduce the coefficient of thermal expansion (“CTE”) mismatch problems. Typically, the compliant layer includes an elastomeric layer which, in the finished package, is disposed between the chip carrier and the face surface of the chip. The compliant layer provides resiliency to the individual terminals, allowing each terminal to move in relation to its electrically connected chip contact to accommodate CTE mismatch as necessary during testing, final assembly and thermal cycling of the device.
In some arrangements used heretofore, the compliant layer is formed by stenciling a thermoset resin onto the chip carrier and then curing the resin. Next, additional resin is applied to the exposed surface of the cured layer, this additional resin is partially cured, and the resulting tacky adhesive surface was used to bond the elastomeric layer to the chip and chip carrier. Once attached, the entire structure is heated and fully cured. The leads are then bonded to respective chip contacts. An encapsulant material is then disposed under and around the leads from the terminal side of the assembly. This process amounts to very carefully depositing a controlled amount of encapsulant on the periphery of the contact surface of the chip from the terminal side of the assembly, building layer upon layer of encapsulant until the leads are fully encapsulated. In such a process, the encapsulant is held in place by the surface tension of the encapsulant material between the dielectric layer and the contact bearing surface of the chip. Using such a method, the encapsulant material may creep on to the exposed surface of the dielectric layer potentially contaminating the terminals and also overcoming the surface tension of the encapsulant further causing the encapsulant to get onto other surfaces of the assembly or onto adjacent chip assemblies.
Another issue associated with some arrangements used heretofore is the use of a prefabricated support structure or ring gird. A prefabricated support structure may be disposed around the chip, generally before the encapsulation step, in order to planarize and/or rigidize the package, especially if the package has only “fan-out leads” or a combination of “fan-in leads” and “fan-out leads”. By the term “fan-in leads” we mean that one end of the lead is connected to a portion of the chip carrier which is disposed directly beneath the chip. By the term “fan-out leads” we mean that one end of the lead is connected to a portion of the chip carrier which is not disposed directly under the chip. Whether the leads fan-in or fan-out, A semiconductor chip package will typically include means for interconnecting the leads to connection points on an external circuit, such as, for example, an array of solder balls. When such packages include fan-out leads, one or more rows of such solder balls are typically disposed outside the periphery of the semiconductor chip, and a support structure should be used to support such solder balls.
The support rings and ring grids used heretofore are typically manufactured in molding, stamping or etching processes. If the support structure or ring grid is prefabricated, such prefabricated component must be designed and manufactured specifically to accommodate the size, shape and arrangement of chips to be packaged. A different support structure may be needed for each type of chip to be packaged and, if a plurality of chips are to be packaged simultaneously using a ring grid, a new ring grid design may be needed each time the arrangement of chips is changed or modified.
Accordingly, new methods of encapsulating semiconductor chip assemblies without using prefabricated support structure or ring grids are desirable.
SUMMARY OF THE INVENTION
The present invention provides a method of packaging a semiconductor chip using a support structure or ring grid made in situ.
The method according to the present invention includes a method of packaging a plurality of semiconductor chips using dispensed support structures. First a sheet-like substrate having a first surface and a plurality of terminals disposed on the first surface is provided. A plurality of chips, each having a face surface with a plurality of contacts disposed thereon, is juxtaposed with the first surface of the substrate. In preferred embodiments, a compliant spacer layer is disposed between the substrate and the chips. The terminals are then electrically connected to contacts on the chips using leads, preferably such that at least some of the leads associated with each chip are fan-out leads. The leads are preferably flexible. A first composition is dispensed onto the substrate in a ring-like pattern around each chip, such that a gap is formed between each ring-like pattern and each chip. The ring-like patterns are cured to form support structures. The ring-like patterns may be positioned such that upon cure, the resulting support structures are interconnected and form a ring grid. A second composition is dispensed into the gaps to encapsulate the leads and at least one surface of each chip, thereby forming an interconnected plurality of packaged semiconductor chips. In preferred methods, the interconnected chips are then diced or singulated to form a plurality of individual semiconductor chips. The support structures may be conductive (electrically or thermally) or insulative. The support structures may have continuous, uniform sidewalls or may have segmented and/or non-continuous sidewalls. In preferred embodiments, such segmented or non-continuous sidewalls are adapted to facilitate the flow of second composition to encapsulate the chips. Introduction and further may be segmented to facilitate introduction of the second composition into the gaps and/or to allow a plurality of chips to be encapsulated using just one or a few dispensers. The support structures are preferably rigid. In preferred embodiments, the support structure is rigid. The foregoing and other objects and advantages of the present invention will be better understood from the following Detailed Description of the Preferred Embodiments, taken together with the attached figures.
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patent: 3811183 (1974-05-01), Celling
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patent: 4143456 (
Beroz Masud
Fosberry Jennifer
Michael Mihalis
Osborn Philip
Jones Josetta
Lerner David Littenberg Krumholz & Mentlik LLP
Niebling John F.
Tessera Inc.
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