Method of manufacturing a plural unit high frequency transistor

Details Method of manufacturing a plural unit high frequency transistor Method of manufacturing a plural unit high frequency transistor

2001-10-11

2003-05-20

Cao, Phat X. (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S341000, C257S536000

Reexamination Certificate

active

06566185

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, to a power transistor especially used to amplify ultra high frequencies, that is, a semiconductor device having a plurality of transistor units with a so-called multi-finger structure each of which is constituted by an interdigital electrode, and a unit prepared by arranging a plurality of unit cells each made up of a drain, gate, and source to be adjacent to each other, and a method of manufacturing the same.
Compact, lightweight devices with high efficiency are demanded for semiconductor devices for amplifying high-frequency signals of several hundred MHz or more, e.g., high-frequency power transistors used on the transmission stage of a portable telephone. Particularly, high-frequency power transistors used in a portable telephone using a battery as a power source must be reduced in power amplification circuit current and increased in amplification efficiency.
To meet these demands, there is proposed a power transistor having a multi-finger structure in which a plurality of unit cells each made up of a drain, gate, and source are arranged adjacent to each other, and the drain and gate are alternately connected to comb finger electrodes, thereby forming a field effect transistor (FET) (e.g., Japanese Utility Model Laid-Open No. 51-80063).
FIG. 19
shows the arrangement of an FET having a multi-finger structure with such comb finger electrodes.
Unit cells each made up of a drain, gate, and source are arranged adjacent to each other on the major surface of a semiconductor substrate. The gate and drain of each unit cell are respectively connected to comb-finger-shaped gate and drain finger electrodes
8
and
12
.
The source of each unit cell is connected to a p
+
-implanted layer (not shown in
FIG. 19
) via a source contact
1
d
and an electrode
2
immediately above the source.
Each gate finger electrode
8
is connected to a gate extraction electrode
12
b
, and each drain finger electrode
12
is connected to a drain extraction electrode
12
a
. The gate and drain extraction electrodes
12
b
and
12
a
are respectively connected to gate and drain pads
22
and
21
for connecting bonding wires.
An FET constituted by a plurality of unit cells arranged adjacent to each other, the comb finger gate electrode (the gate finger electrodes
8
and gate extraction electrode
12
b
), and the comb finger drain electrode (the drain finger electrodes
12
and drain extraction electrode
12
a
) is called a transistor unit
30
.
To obtain a large output from a power transistor, the finger length and the number of finger electrodes are increased in a power transistor having this multi-finger structure, thereby increasing the gate width of the whole element.
However, a long gate finger increases the gate resistance and degrades high-frequency characteristics. If the number of finger electrodes is increased, the chip becomes elongated, and high-frequency characteristics are degraded by a phase shift between finger electrodes.
To solve these problems, a semiconductor device having the conventional multi-finger structure achieves a high output by arranging a plurality of transistor units and increasing the gate width. At the same time, the area efficiency is increased by laying out the gate and drain pads of respective transistor units close to each other.
There is further provided a semiconductor device having a so-called fishbone structure in which a pair of transistor units share a gate extraction electrode to increase the degree of integration.
FIG. 20
shows an example of the arrangement of a power transistor having such a fishbone structure.
A pair of transistor units are constituted by a gate extraction electrode
12
b
which extends between a pair of two units each prepared by arranging a plurality of unit cells each made up of a drain, gate, and source adjacent to each other, and which is commonly connected to gate finger electrodes
8
of respective unit cells, and two drain extraction electrodes
12
a
each of which extends to a position where the drain extraction electrode
12
a
faces the gate extraction electrode
12
b
and a corresponding unit, and which is commonly connected to drain finger electrodes
12
of the unit.
This structure is called a fishbone structure from the shape of the gate extraction electrode
12
b
commonly connected to the gate finger electrodes
8
.
Note that the fishbone structure also includes a structure having one drain extraction electrode and two gate extraction electrodes, in addition to the above structure having one gate extraction electrode and two drain extraction electrodes. In other words, a structure having a drain extraction electrode which extends between a pair of units and is commonly connected to drain finger electrodes of respective unit cells, and two gate extraction electrodes each of which extends to a position where the gate extraction electrode faces the drain extraction electrode and a corresponding unit, and is commonly connected to gate finger electrodes
8
of the unit is also called a fishbone structure.
One end of the gate extraction electrode
12
b
is connected to a gate pad
22
for connecting a boding wire. The two drain extraction electrodes
12
a
are commonly connected to one drain pad
21
at an end opposite to the gate pad
22
.
This structure in which two transistor units share the gate extraction electrode
12
b
and the two drain extraction electrodes
12
a
are commonly connected to one drain pad
21
is called a transistor unit pair or fishbone cell.
The power transistor in this example is constituted by arranging parallel a plurality (four in
FIG. 20
) of transistor unit pairs which share a gate extraction electrode.
The power transistor may be constituted by arranging parallel a plurality of transistor unit pairs (fishbone cells) each having one drain extraction electrode and two gate extraction electrodes.
To prevent oscillation and stabilize operation in a conventional semiconductor device having a plurality of transistor unit pairs, adjacent gate pads
22
are connected by gate extraction electrode connection wiring lines
23
made of a conductor such as Al, and adjacent drain pads
21
are connected by drain extraction electrode connection wiring lines
24
, as shown in FIG.
20
.
However, oscillation cannot always be prevented even if a plurality of transistor unit pairs (or transistor units) are connected by conductors. In particular, the semiconductor device tends to oscillate with a large number of transistor unit pairs (or transistor units) and a large total gate width.
For example,
FIG. 21
shows a graph of static characteristics of the drain current in the semiconductor device formed on an Si substrate with the arrangement shown in
FIG. 20
when the gate width is 40 mm, and gate or drain pads are connected to each other. In
FIG. 21
, the abscissa and ordinate respectively represent the drain voltage and drain current using the gate voltage as a parameter. Although the drain current increases together with the gate voltage, the semiconductor device oscillates to distort the drain voltage vs. drain current graph.
The semiconductor device made up of a plurality of transistor unit pairs (or transistor units) oscillates because operation states are different between respective transistor unit pairs (or transistor units) even within a single chip, and this unbalance increases phase interference between the transistor unit pairs (or transistor units). Oscillation arising from this phase interference is called loop oscillation.
In the conventional semiconductor device, even if gate or drain pads are connected to each other, and one of the pads fails to be connected by a bonding wire, this error of the semiconductor device cannot be detected by DC screening. To detect a bonding error critically influencing a high-frequency operation of the semiconductor device, time-consuming, high-cost, radio frequency (RF) screening must be conducted.
SUMMARY OF THE

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