Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-12-15
2001-06-26
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S199000, C438S201000, C257S069000, C257S204000, C257S206000
Reexamination Certificate
active
06251729
ABSTRACT:
BACKGROUND OF THE OF THE INVENTION
The invention relates to a method of manufacturing a semiconductor device comprising a semiconductor body which is provided at a surface with a field-effect transistor having a gate insulated from the semiconductor body by a gate dielectric, and with a non-volatile memory element having a floating gate and a control gate, the floating gate being insulated from the semiconductor body by a floating gate dielectric and from the control gate by an inter-gate dielectric, by which method a first and a second active region of a first conductivity type adjoining the surface are defined in the semiconductor body for the transistor and the memory element, respectively, and the surface is coated with a first insulating layer providing the floating gate dielectric of the memory element, on which first insulating layer a silicon-containing layer is applied providing the floating gate of the memory element, after which source and drain zones of a second conductivity type of the memory element are provided in the semiconductor body and a second insulating layer is applied at the second active region so as to provide the inter-gate dielectric of the memory element, on which second insulating layer a conductive layer is applied providing the control gate of the memory element.
A method of manufacturing a semiconductor device of the kind mentioned in the opening paragraph is known from U.S. Pat. No. 5,340,764. In the known method, a first series of steps is performed to manufacture the non-volatile memory element consisting of two stacked layers of polycrystalline silicon (called poly hereinafter for short), which are mutually separated by an inter-gate dielectric and insulated from the semiconductor body by a floating gate oxide. After formation of the non-volatile memory element, a second series of steps is performed to manufacture the field-effect transistor. For this purpose a relatively thin gate oxide layer is applied, which is covered by a further poly layer providing the gate of the field-effect transistor. After patterning of, this poly layer, the field-effect transistor is provided with a source and a drain zone by means of a self-aligned implantation using the gate together with adjacent oxide field insulating regions as a mask.
Conventionally, a self-aligned implantation consists of an actual implantation of atoms into the semiconductor body followed by an anneal or so-called drive-in step, which is often carried out at a temperature as high as 1000° C. in order to activate the as-implanted atoms and to repair implantation damage caused to the lattice of the semiconductor body.
A disadvantage of the known method is that the control gate and the inter-gate dielectric of the memory element as well as the gate and the gate dielectric of the transistor are applied prior to the self-aligned implantation of the source and the drain zone of the transistor, and, hence, are subjected to the high-temperature anneal following the actual implantation. Consequently, serious constraints are imposed on the choice of process compatible materials for the gate and the control gate as well as for the gate dielectric and the inter-gate dielectric. A further disadvantage of the known method is that it possesses a rather complex sequential character so as to achieve a separate device optimization for the non-volatile memory element and the field-effect transistor.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a method of manufacturing a semiconductor device of the kind mentioned in the opening paragraph which increases the flexibility as regards the use of process compatible materials for the logic device and the non-volatile device in a conventional CMOS process sequence, and which allows a separate optimization of the logic device characteristics and the non-volatile device characteristics without the complexity of the process sequence being substantially increased.
According to the invention, this object is achieved in that, together with the formation of the floating gate and the floating gate dielectric of the memory element, the first active region is provided with a sacrificial gate and a sacrificial gate dielectric of the transistor, respectively, after which source and drain zones of the second conductivity type of the transistor are provided together with the source and drain zones of the memory element and a dielectric layer is applied which is removed over at least part of its thickness by means of a material removing treatment until the silicon-containing layer at the first and the second active region is exposed, after which the silicon-containing layer and the first insulating layer at the first active region are removed, thereby forming a recess in the dielectric layer, in which recess a third insulating layer is applied providing the gate dielectric of the transistor at the first active region, after which the conductive layer is applied, thereby filling the recess at the first active region, which conductive layer is shaped into the gate of the transistor at the first active region and into the control gate of the memory element at the second active region.
The above measures in accordance with the invention prevent the gate and the gate dielectric of the transistor as well as the control gate and the inter-gate dielectric of the memory element, once formed, from being exposed to the high temperatures, often as high as 1000° C., of the drive-in step carried out after the actual source/drain implantation. This substantially increases the flexibility in the use of process compatible materials for the gate and control gate and for the gate dielectric and inter-gate dielectric into conventional CMOS technology. Moreover, the method in accordance with the invention allows a separate optimization of logic device characteristics and non-volatile device characteristics in conventional CMOS technology while using as many common process steps as possible, thereby reducing the complexity of the process.
The above advantages are achieved by initially providing the field-effect transistor with a sacrificial gate and a sacrificial gate dielectric while at the same time providing the memory element with a floating gate and a floating gate dielectric, and by replacing in a later stage of the process, with the high-temperature anneal associated with the self-aligned implantation of the source and drain zones having been being carried out already, the sacrificial gate and the sacrificial gate dielectric with an actual gate and an actual gate dielectric while at the same time providing the memory element with a control gate and an inter gate dielectric.
The replacement of the sacrificial gate by the actual gate shows a similarity to the replacement gate process described in an article entitled “Sub-100 nm gate length metal gate NMOS transistors fabricated by a replacement gate process”, written by Chatterdee et al. and published in IEDM 97 (1997), pp. 821-824. A typical characteristic of the replacement gate technology is that the actual gate is built self-aligned to the source/drain zones with all high temperature anneals performed before the formation of the actual gate.
The sacrificial gate of the transistor and the floating gate of the memory element are formed from a silicon-containing layer comprising polycrystalline silicon, or possibly amorphous silicon or Ge
x
Si
(1−x)
with x the fraction of germanium lying in a range between 0 and 1. Prior to the removal of the sacrificial gate of the transistor a relatively thick dielectric layer is applied covering the sacrificial gate of the transistor and the floating gate of the memory element. The dielectric layer is then removed by means of, for example, chemical-mechanical polishing over at least part of its thickness until the sacrificial gate and the floating gate are exposed. Subsequently, the sacrificial gate of the transistor is removed by means of selective etching. After the removal of the sacrificial gate a dip-etch is carried out in order to remove the subjacent sacrificial gate d
Montree Andreas H.
Schmitz Jurriaan
Woerlee Pierre H.
Biren Steven R.
Dang Trung
Kebede Brook
U.S. Philips Corporation
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