Method of manufacturing a non-volatile memory and a CMOS transis

Details Method of manufacturing a non-volatile memory and a CMOS transis Method of manufacturing a non-volatile memory and a CMOS transis

1998-03-19

2000-05-30

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438258, H01L 218247

Patent

active

06069033&

ABSTRACT:
The invention provides a method of combining an EPROM (or EEPROM) with a standard CMOS process. After growing the gate oxide 9, a lightly doped polycrystalline or amorphous silicon layer 10, hereinafter referred to as poly I, is deposited. In this layer, the floating gate 13 of the memory cells is defined, while, outside the memory matrix, the surface remains covered with poly I. Subsequently, the source/drain implantation in the memory cells is carried out. The poly layer 10 situated outside the memory matrix is masked against this heavy implantation by the mask 11. Subsequently, a second poly layer can be provided from which the control gates of the memory cells are formed and which forms a coherent layer with the existing poly I layer outside the matrix. In a subsequent series of steps in a standard CMOS process, the n-ch MOSTs and p-ch MOSTs are provided, n-type gates 22 for the n-ch MOSTs and p-type gates 23 for the p-ch MOSTs being formed from the poly I layer.

REFERENCES:
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patent: 5223451 (1993-06-01), Uemura et al.
patent: 5395778 (1995-03-01), Walker
patent: 5449634 (1995-09-01), Inoue
patent: 5472892 (1995-12-01), Gwen et al.

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