Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-07-28
2004-11-23
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S266000, C438S257000, C257S321000
Reexamination Certificate
active
06821850
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a multi-level flash EEPROM-cell and a method of manufacture thereof; particularly to a multi-level EEPROM cell and a method of manufacture thereof capable of improving a program characteristic of the multi-level cell by employing a first and a second control gates whose parts are overlapped to each other and which overlie the top of a floating gate.
DESCRIPTION OF THE PRIOR ART
A flash EEPROM is getting popular since it has a lot of unique advantages. An obstacle preventing the flash EEPROM from being popular is that a high cost is required for a unit of information. In order to overcome the above drawback, manufacturing companies focus on increasing the integration of a cell. Since, however, a structure of the flash EEPROM is much complicated compared with that of a DRAM, there is a difficulty in the cell integration.
In a Strata Flash introduced by Intel corporation, which employs multi-level cells therein, a multi-level cell is programmed to a desired level through a process slowly implanting a small amount of electrons, e.g., about 3000 numbers of electrons, into the cell. Therefore, it takes a long time until the cell is programmed to the highest level.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a multi-level EEPROM cell and a method of manufacture thereof capable of improving a program characteristic of the multi-level cell through the use of a first and a second control gates that are partially overlapped with each other and overlies the top of a floating gate.
In accordance with one aspect of the present invention, there is provided a multi-level flash EEPROM cell comprising: a floating gate formed as being electrically separated from a silicon substrate by an underlying tunnel oxide layer; a first dielectric layer formed over the top of the floating gate; a first control gate formed on the floating gate as being electrically separated from the floating gate by the first dielectric layer; a second dielectric layer formed on the sidewall and top of the first control gate; a second control gate formed on the sidewall and top of the first control gate as being electrically separated from the first control gate by the second dielectric layer; and a source and drain formed in the substrate as being self-aligned with both edges of the second control gate.
In accordance with another aspect of the present invention, there is provided a method for manufacturing a flash EEPROM cell comprising the steps of: patterning a first polysilicon layer after forming a tunnel oxide layer on a silicon substrate; forming a first dielectric layer on the top of the first polysilicon layer; making a part of a first control gate by depositing a second polysilicon layer on the top of the first dielectric layer; depositing a second dielectric layer on a sidewall of the first control gate; forming a second control gate by depositing a third polysilicon layer on the top of the second dielectric layer; and forming a source and a drain by using a source/drain ion implantation process which is fulfilled with a self-aligned etching technique.
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EPO Search Report, dated Nov. 1, 2001, regarding Application No. GB 0031118.3.
Chang Sang-Hoan
Kim Ki-Seog
Lee Keun-Woo
Park Sung-Kee
Elms Richard
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Hyundai Electronics Industries Co,. Ltd.
Smith Brad
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