Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2002-07-19
2004-01-06
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S200000, C438S257000
Reexamination Certificate
active
06673705
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-200257, filed Jun. 30, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device including MISFET (Metal Insulator Semiconductor Field Effect Transistor) having a plurality of post-oxide films differing from each other in thickness, which are formed in the same chip used in a large scale integrated circuit (LSI) and a method of manufacturing the same.
In an SOC (System On a Chip) or a system LSI, various MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) are formed in a chip. A relatively high power source voltage, e.g., 3.3V, 2.5V, 1.8V, is required in an input-output circuit, a mixed DRAM circuit or a mixed analog circuit. On the other hand, a MOSFET having a long gate and a relatively thin gate insulating film and driven by a relatively low power voltage, e.g., 1.5V, 1.2V, 1.0V, is used in a logic (digital) circuit or a mixed SRAM circuit in order to minimize the MOSFET delay.
Also, MOSFETs having different characteristics, i.e., a MOSFET for gate load driving and another MOSFET for wiring load driving, are formed as MOSFETs driven by same power source voltage, which are included in the same logic (digital) circuit. The MOSFET for gate load driving is required to include a MOSFET section having a low load capacitance in order to drive multi-stage CMOS transistors. Also, MOSFETs for wiring load driving are required to have a high drain current for driving the multi-wiring layer.
Concerning the circuit requiring a high power source voltage, the gate insulating film is allowed to have a plurality of regions differing from each other in thickness in order to cope with the situation described above. However, if the gate insulating film is allowed to have a plurality of regions differing from each other in thickness, problems are generated as follows. Specifically, where a post-oxide film adapted for the low voltage MOSFET and the conditions of the source-drain extension are used in the high voltage system, problems tend to be generated in the drain breakdown voltage, the hot carrier breakdown voltage, the GIDL (Gate Induced Drain Leakage Current) and the PN tunneling current.
If the drain design is made the same, the following problems are generated concerning the circuit driven with a low power source voltage. Specifically, in a MOSFET for gate load driving, it is desirable for the parasitic capacitance such as the mirror capacitance and the junction capacitance to be minimized. On the other hand, in a MOSFET for wiring load driving, it is desirable to increase the drain current even if the extension is formed deep, so as to increase the mirror capacitance. It follows that a MOSFET for gate load driving and a MOSFET for wiring load driving are considered to be different from each other in the optimum conditions for the post-oxide film and the source-drain extension.
As described above, in the conventional semiconductor device, it was difficult to form a single integrated circuit under a single condition.
BRIEF SUMMARY OF THE INVENTION
An object of the present invention, which has been achieved for solving the above-noted problems inherent in the prior art, is to provide a semiconductor device having an optimum MISFET structure in a single integrated circuit which can cope with varying operating conditions and to provide a method of manufacturing the particular semiconductor device.
According to a first aspect of the present invention, there is provided a semiconductor device including first and second MISFETs, each of the first and second MISFETs comprising a semiconductor substrate common to the first and second MISFETs; a source region formed in the semiconductor substrate; a drain region formed in the semiconductor substrate apart from the source region; a gate insulating film provided on the surface of the semiconductor substrate and positioned between the source region and the drain region; a gate electrode provided on the gate insulating film; and a covering insulating film having a first region arranged on the source region and the drain region and a second region arranged on the side surfaces of the gate electrode and the gate insulating film, the first region in the first MISFET differing in thickness from the first region in the second MISFET.
According to a second aspect of the present invention, there is provided a semiconductor device including first and second MISFETs, each of the first and second MISFETs comprising: a semiconductor substrate common to the first and second MISFETs; a source region formed in the semiconductor substrate; a drain region formed in the semiconductor substrate apart from the source region; a gate insulating film provided on the surface of the semiconductor substrate and positioned between the source region and the drain region; a gate electrode provided on the gate insulating film; and a covering insulating film having a first region arranged on the source region and the drain region and a second region arranged on the side surfaces of the gate electrode and the gate insulating film, the first and second region in the first MISFET differing in thickness from the first and second region in the second MISFET.
According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device including first and second MISFETs comprising the steps of: providing gate insulating films of the first and second MISFETs on a semiconductor substrate; providing gate electrodes on the gate insulating films; covering the gate electrodes of the first and second MISFETs with an insulating material film, the material film providing the basis of a covering insulating film having a first region arranged on the semiconductor substrate and a second region arranged on the side surfaces of the gate electrode and the gate insulating film in the first and second MISFETs; decreasing the thickness of the insulating material film by etching in a region corresponding to the first region of the covering insulating film in the first MISFET; and forming after the etching step a source region and a drain region in the surface region of the semiconductor substrate by ion implantation through the first region of the covering insulating film with the gate electrode used as a mask in the first and second MISFETs.
According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device including first and second MISFETs comprising the steps of: providing gate insulating films of the first and second MISFETs on a semiconductor substrate; providing gate electrodes on the gate insulating films; covering the gate electrode of the first and second MISFETs with a first insulating material film, the first insulating material film providing the basis of a covering insulating film having a first region arranged on the semiconductor substrate and a second region arranged on the side surfaces of the gate electrode and the gate insulating film in the second MISFET; removing the first insulating material film from the first MISFET; covering, after removal of the first insulating film, the gate electrode of the first MISFET with a second insulating material film, the second insulating material film providing the basis of a covering insulating film having a first region arranged on the semiconductor substrate and a second region arranged on the side surfaces of the gate electrode and the gate insulating film in the first MISFET; and forming after the gate electrode of the first MISFET is covered with the second insulating material film, a source region and a drain region in the surface region of the semiconductor substrate by ion implantation through the first region of the covering insulating film with the gate electrode used as a mask in the first and second MISFETs.
According to a fifth aspect of the present invention, there is provided a
Huynh Yennhu B
Jr. Carl Whitehead
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