Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-03-30
2001-05-22
Bowers, Charles (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S201000, C438S203000, C438S234000, C438S262000, C438S263000
Reexamination Certificate
active
06235588
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a MOS transistor and more specifically a MOS transistor belonging to a memory point.
The present invention applies in particular to the manufacturing of memory points compatible with conventional CMOS transistor manufacturing methods.
2. Discussion of the Related Art
Floating gate memory points in which the control gate is formed of a layer diffused in a silicon substrate are known. Floating gate memory points with a single polysilicon level may thus be formed. An example of such a memory point is shown in
FIG. 1. A
MOS transistor T includes a drain region D and a source region S of type N
+
formed in a P-type silicon substrate on either side of a gate G formed of a portion of a polysilicon region
10
. Besides, polysilicon region
10
extends over a region
11
where it is arranged above an N
+
-type region
12
formed in the substrate. Of course, when a P-type silicon substrate is mentioned, it may be a proper substrate, or an epitaxial layer on a silicon substrate, or a P-type well formed in a substrate. To simplify, the various connections have not been shown in
FIG. 1. A
drain terminal connected to region D, a source terminal connected to region S, and a control terminal connected to region
12
should clearly be provided. Such structures are well known in the art and will not be described in further detail hereafter. It should be understood that polysilicon region
10
forms a floating gate of transistor T, this floating gate being capacitively coupled with a control gate
12
. The manufacturing method used will essentially be studied.
Conventionally, N
+
-type region
12
is first formed in the P substrate, possibly at the same time as other regions of the integrated circuit in which the considered structure is formed. Then, after forming, in various locations silicon oxides of appropriate thicknesses, polysilicon region
10
is deposited and etched to form on the one hand region
11
capacitively coupled with control gate
12
, and on the other hand, gate G of MOS transistor T. After this, the drain and source regions of the transistor are formed by using, in particular, the gate as a mask. Conventionally, these regions are formed in one or several steps with or without using spacers. It should be noted, especially for so-called flash memories, that the gate oxide under gate portion G is a tunnel oxide of small thickness and that the drain and source regions extend at least partially under the gate.
These various methods have been optimized essentially to promote the constitution of memory points, a great number of which are desired to be formed in a same chip. However, a disadvantage of these methods is to require a great number of manufacturing steps, especially when the source and drain regions are formed from several successive implantations.
SUMMARY OF THE INVENTION
Thus, an object of the present invention is to provide a simple method of manufacturing a floating gate memory point having a single polysilicon level, more specifically realizable by only using the steps conventionally provided for the manufacturing of a CMOS-type or BICMOS-type integrated circuit.
To achieve these objects as well as others, the present invention provides a method of manufacturing a MOS transistor, including the steps of defining, by means of a first resist mask, N-type drain and source implantation areas; removing the first mask and diffusing the implanted dopant; annealing, whereby a thicker oxide forms above the source and drain regions than above the central gate insulation area; forming a polysilicon finger above the central gate insulation portion to form the gate of the MOS transistor; and performing a second source/drain implantation.
According to an embodiment of the present invention, a second source/drain implantation is preceded by the forming of spacers.
According to an embodiment of the present invention, the gate finger is prolonged by a polysilicon region forming a capacitive coupling with a doped region formed in the substrate at the same time as the first N-type dopant implantation.
The present invention provides such a method compatible with the making of a BICMOS-type structure, in which the initial source/drain implantation and the implantation of the capacitive coupling region are performed at the same time as the collector well implantations of the NPN bipolar transistors.
According to an embodiment of the present invention, the transistor is formed in a well completely insulated by regions of the opposite type of conductivity.
The foregoing objects, features and advantages of the present invention, will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.
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patent: 5248624 (1993-09-01), Icel et al.
patent: 5414291 (1995-05-01), Miwa et al.
patent: 5429960 (1995-07-01), Hong
patent: 5643812 (1997-07-01), Park
patent: 5814857 (1998-09-01), Park
patent: 5834352 (1998-11-01), Choi
patent: 195 31 629 (1997-01-01), None
patent: 0 780 902 (1997-06-01), None
French Search Report from French Patent Application 98/04209, filed Mar. 31, 1998.
Bowers Charles
Galanthay Theodore E.
Lee Hsien-Ming
Morris James H.
STMicroelectronics S.A.
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