Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-10-12
2003-04-15
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S234000, C438S350000
Reexamination Certificate
active
06548337
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of forming a high gain bipolar junction transistor with a counterdoped base region using existing CMOS technology.
BACKGROUND OF THE INVENTION
In mixed signal applications it is sometimes necessary to have CMOS transistors and bipolar junction transistors (BJT) on the same chip or integrated circuit. Currently, integrating these devices on the same chip requires additional processes and a compromise in the performance of one or both types of devices. This compromise is necessary because the doping concentrations of the various well regions that are necessary to optimize the performance of the CMOS transistors will adversely affect the performance of the bipolar junction transistors (BJTs) present on the chip. Illustrated in
FIG. 1
is a cross-section of a portion of an integrated circuit showing a PMOS transistor
12
and a NMOS transistor
14
. The PMOS transistor
12
is formed in a n-well region
30
and the NMOS transistor
14
is formed in a p-well region
20
. Both n-well
30
and p-well
20
regions are formed in a semiconductor substrate
10
using doping techniques such as ion implantation and diffusion. In most cases the semiconductor substrate
10
will be doped p-type but n-type doped substrates can also be used. Isolation is provided in the substrate using localized oxidation (LOCOS) or shallow trench isolation (STI). Shown in
FIG. 1
is an example of STI isolation structures
40
which are formed by first etching a trench in the substrate
10
and then filling the trench with an insulating material such as silicon oxide, silicon nitride or both. A gate dielectric material
50
is formed on the substrate which will form the gate dielectric for the NMOS transistor
14
and the PMOS transistor
12
. A conducting gate material is formed and patterned to form the PMOS transistor gate
60
and the NMOS transistor gate
65
. Prior to the formation of the transistor sidewall structures
70
, drain and source extension regions can be formed if required. The transistor sidewall structures are typically formed by first performing a conformal blanket deposition of a insulating dielectric followed by an anisotropic etch to form the sidewalls
70
. Silicon nitride or silicon oxide is the insulating dielectric films typically used for sidewall formation. The PMOS transistor source region
90
and drain region
95
are formed by implanting p-type dopant species such as boron or BF
2
into the substrate adjacent to the sidewall structures
70
. Thus for the PMOS transistor the source and drain regions
90
and
95
are p-type. The NMOS transistor source region
80
and drain region
85
are formed by implanting n-type dopant species such as arsenic and phosphorous into the substrate adjacent to the gate structure. Thus for the NMOS transistor the source and drain regions
80
and
85
are n-type.
In addition to the NMOS and PMOS transistors described above, CMOS integrated circuits also contain parasitic BJT devices. As shown in
FIG. 1
, a parasitic PNP BJT transistor is formed by the p-type drain region
95
of the PMOS transistor
12
, the n-well region
30
and the p-well region
20
. Similarly a parasitic NPN BJT is formed by the source region
80
of the NMOS transistor
14
, the p-well region
20
and the n-well region
30
. Thus the base of the parasitic NPN transistor is connected to the collector of the parasitic PNP transistor and vice versa. During normal operation of the CMOS circuit when various voltages are applied to the gate, source, drain, and well regions of the PMOS and NMOS transistors, proper operation of the CMOS circuit requires that the gain of the parasitic NPN and PNP transistors be less than one. If the gain of these parasitic transistors is greater than one latch-up of the CMOS circuit will occur and the CMOS circuit will cease to function. Therefore optimized CMOS circuits do not contain high gain parasitic BJTs. As stated above, certain circuit applications require both CMOS transistors and high gain BJTs on the same chip. There is therefore a need to form integrated high gain BJTs in optimized CMOS circuits without adding costly processing steps and process complexity.
SUMMARY OF INVENTION
The invention relates to a method of forming a high gain bipolar junction transistor with a counterdoped base region using existing CMOS technology. The bipolar junction transistor comprises a compensated base region which is formed by forming the p-well region and the n-well region in a common substrate region. In particular the method comprises: providing a semiconductor substrate; forming a p-well region in said semiconductor substrate by performing p-well ion implantation comprising p-type dopant species; forming a n-well region in said semiconductor substrate by performing n-well ion implantation comprising n-type dopant species; and forming a compensated base region of said bipolar junction transistor by allowing said p-well ion implantation and said n-well ion implantation to enter a common region of said semiconductor substrate.
REFERENCES:
patent: 6001701 (1999-12-01), Carroll et al.
patent: 6117718 (2000-09-01), Hwang et al.
patent: 6127213 (2000-10-01), Tung
Aragon Michael D.
Benaissa Kamel
Shen Chi-Cheong
Spratt David B.
Brady III W. James
Instruments Incorporated
McLarty Peter K.
Nguyen Tuan H.
Telecky , Jr. Frederick J.
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