Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-10-09
2001-02-13
Wilczewski, Mary (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S591000
Reexamination Certificate
active
06187633
ABSTRACT:
BACKGROUND OF THEE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a gate structure for a semiconductor memory device. More specifically the invention relates to a method for improving upon the electrical properties provided by an ONO intergate dielectric.
2. Discription of the Related Art
In conventional semiconductor memory devices an “ONO” dielectric film is used as an intergate having a stacking structure consisting of a silicon oxide film/a silicon nitride film/a silicon oxide film. The ONO structure provides good withstanding voltage and retention characteristic with a relatively thin film.
However, semiconductor device manufacturers are continually pressured to increase effective device densities in order to remain cost competitive. As the ONO dielectric film becomes thinner, pinholes and poor electrical qualities charateristic of nitride cause low breakdown voltages and leakage adversly affecting the reliability of the memory device.
Accordingly, a need exists for an intergate dielectric film for use in semiconductor memory devices that can provide higher withstanding voltage and retention characteristics as the film thickness is reduced.
The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 5,661,056 (Takeuchi) discloses oxynitride forme on the oxide layer of an NO and NON dielectric stacks.
U.S. Pat. No. 5,597,754 (Lou et al.), U.S. Pat. No. 5,427,967 (Sadjadi) and U.S. Pat. No. 5,665,620 (Nguyen) disclose methods to form ONO stacks.
U.S. Pat. No. 5,443,998 (Meyer) discloses a method of forming a chlorinated ONO stack.
U.S. Pat. No. 5,407,870 (Okada) discloses an oxynitride/oxide/oxynitride stack.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide improved electrical properties (particularly withstanding voltage and leakage) over a conventional ONO stacked intergate dielectric layer.
It is another object of the present invention to provide a structure and a process for fabricating an improved semiconductor memory device gate having higher withstanding voltage and lower leakage than is provided by a conventional ONO stacked intergate dielectric layer of comparable thickness.
It is another object of the present invention to reduce or eliminate the pinhole problem found in the nitride layer of a conventional ONO stacked dielectric layer.
It is yet another object of the present invention to reduce the structural stress as compared to a conventional ONO stacked dielectric layer.
To acheive the above objects, the present invention provides a semiconductor memory device gate comprising: source and drain regions spaced apart from each other on a semiconductor substrate of one conductivity type and having a conductivity type opposite to the conductivity type of the semiconductor substrate; a tunnel oxide over a channel region between the source and drain regions; a floating gate electrode over the tunnel oxide; an intergate dielectric consisting of successive layers of silicon oxide, silicon nitride, silicon oxynitride and silicon oxide over the floating gate electrode; and a control gate electrode over the intergate dielectric.
Further, the present invention provides a method of manufacturing a semiconductor memory device gate. The method begins by forming a first insulating layer (
12
) on a semiconductor substrate (
10
) having one conductivity type. A first conductive layer (
14
) is formed on the first insulating layer (
12
). A second insulating layer is formed on the first conductive layer (
14
) by sequentially stacking: a first silicon oxide layer (
16
); a silicon nitride layer (
18
); a silicon oxynitride layer (
20
); and a second silicon oxide layer (
22
). A second conductive layer (
24
,
26
&
28
) is formed on the second insulating layer (
16
,
18
,
20
&
22
). The first insulating layer (
12
) is patterned to form a tunnel oxide. The first conductive layer (
14
) is patterned to form a floating gate electrode. The second insulating layer (
16
,
18
,
20
&
22
) is patterned to form an intergate dielectric. The second conductive layer (
24
,
26
&
28
) is patterned to form a control gate. Impurity ions are implanted into the semiconductor substrate (
10
) adjacent to the floating gate electrode (
14
) on both sides to form source and drain regions (
30
&
32
) having a conductivity type opposite to the conductivity type of the semiconductor substrate. A side insulating film is formed on the side surfaces of the floating gate electrode (
14
) and the control gate electrode (
24
,
26
&
28
).
REFERENCES:
patent: 5407870 (1995-04-01), Okada et al.
patent: 5427967 (1995-06-01), Sadjadi et al.
patent: 5443998 (1995-08-01), Meyer
patent: 5460991 (1995-10-01), Hong
patent: 5597754 (1997-01-01), Lou et al.
patent: 5661056 (1997-08-01), Takeuchi
patent: 5665620 (1997-09-01), Nguyen et al.
Dong Zhong
Hui Joe
Zhang Anqing
Chartered Semiconductor Manufacturing Ltd.
Goodwin David
Pike Rosemary L. S.
Saile George O.
Stoffel William J.
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