Method of manufacturing a flash memory device

Details Method of manufacturing a flash memory device Method of manufacturing a flash memory device

2000-11-22

2001-11-13

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S264000

Reexamination Certificate

active

06316313

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to a method of manufacturing a flash memory device, and more particularly to a method of manufacturing a flash memory device capable of reducing a well resistance and a parasitic capacitance in the flash memory device.
BACKGROUND OF THE INVENTION
In general, a well region in a flash memory device is formed through the process by which ions are implanted into a semiconductor substrate and are diffused by thermal process. However, the diffused well region formed by this method has the following drawbacks.
Firstly, the diffused well region has a high well resistance of several &OHgr;~ several hundreds K&OHgr;. Thus, there is a drawback in the erase speed due to delay time RC. This provides the flash memory device with the cause of defeat in competing the speed with DRAM or SRAM.
Secondly, it has a high parasitic capacitance. Most of the flash cells use a triple P-well structure. The reason is to reduce the resistance of the well, by performing erase operation by which a bias is applied to the well in the flash cell. The operating speed of the device is higher as the delay time (=RC) is smaller. However, as some time taken to charge the parasitic capacitance of this structure itself is required, this affects the major cause slowing the operating speed of the device. This causes a problem that a given level of voltage must be maintained in order to charge the parasitic capacitance. Also, it is one of the most important problems in designing a flash memory device such as a charge pump size in a low-voltage flash memory device design.
Thirdly, there is a problem in the erase speed. The smallest unit of erase in the conventional flash cell is a block (or sector) unit, wherein one block is typically 512 Kbits. That is, the conventional flash memory device can be programmed in one cell unit but could not be erased in one cell unit. Also, as the conventional flash memory device could not be erased in one cell unit, it must be erased in one block unit. Thus, when the erase operation is performed, various problems are generated due to a surplus current flowing into a bit line. There is a difficulty in a design for reducing this bit line current.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method of manufacturing a flash memory device capable of improving an electric characteristic of a flash memory device by forming a well region using a metal silicide in the flash memory device.
In order to accomplish the above object, a method of manufacturing a flash memory device according to the present invention is characterized in that it comprises the steps of sequentially forming an oxide film, a pad polysilicon layer, a metal silicide layer, a first un-doped polysilicon layer and a buffer oxide film on a substrate, etching selected regions on the buffer oxide film, the first un-doped polysilicon layer, the metal silicide layer, the pad polysilicon layer and the oxide film, using a first ISO mask, to form a first trench, whereby an unit sector is defined, after forming an intermediate thermal oxide film on the entire structure in which the first trench is formed, flattening the intermediate thermal oxide film until the surface of the buffer oxide film is exposed, thus burying the intermediate thermal oxide film only within the first trench, etching selected regions of the buffer oxide film and the first un-doped polysilicon layer, using a second ISO mask, so that the surface of the tungsten silicide layer can be exposed, to form a second trench, whereby an unit cell is defined, forming a second un-doped polysilicon layer on the entire structures in which the second trench is formed, and then flattening the second un-doped polysilicon layer, and annealing the second un-doped polysilicon layer to crystallize the second un-doped polysilicon layer, and performing a threshold voltage ion implantation process and a well ion implantation process to the entire structure including the crystallized second un-doped polysilicon layer, and then performing a thermal process, whereby a well region is formed.


REFERENCES:
patent: 6187635 (2001-02-01), Kaya
patent: 6207507 (2001-03-01), Wang
patent: 6277689 (2001-08-01), Wong

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