Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-10-27
2001-04-24
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S258000
Reexamination Certificate
active
06221716
ABSTRACT:
FIELD OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a flash memory device. In particular, the present invention relates to a method of manufacturing a flash memory device capable of increasing the coupling ratio and also of improving reliability of hot carriers both at the peripheral circuit area and the cell area upon operation of the device, by which a control gate is formed to surround one side of a floating gate and the source/drain junction of the peripheral circuit area is formed before formation of the drain junction of the memory cell area.
2. Description of the Prior Art
Generally, as degree of integration of the memory device is increased and the operating voltage is lowered, the current flash memory device requires a cell having a higher program operating speed and erase operating speed. In order for the cell have a higher program operating speed and erase operating speed, it is believed that the coupling ration of the cell has to be increased. With the convention cell structure, however, there is a limitation to increase the coupling ratio.
FIG. 1A
shows a layout of a conventional flash memory device, and
FIG. 1B
shows a sectional view of a conventional flash memory device.
Now, the method of manufacturing the conventional flash memory device will be explained by reference to
FIGS. 1A and 1B
.
A field oxide film
20
is formed on a semiconductor substrate
10
to define active regions at the cell area and the peripheral circuit area. Then, a tunneling oxide film
31
is formed on the active region of the cell area. Next, a first polysilicon layer is formed on the entire structure including the tunneling oxide film
31
. Thereafter, the first polysilicon layer is patterned by etching process using a floating gate mask. After a -cell source
35
is formed by injecting the cell source ions, a dielectric film
33
is formed on the entire structure. Then, after a second polysilicon layer is formed on the entire structure including the dielectric film
33
, the second ploysilicon layer, the dielectric film
33
and the first polysilicon layer are sequentially etched by etching process using the control gate mask, thus forming a floating gate
32
and a control gate
34
at the cell area. During these processes, a gate electrode (not shown) is formed at the active region of the peripheral circuit area. A source line
35
A and a cell drain
36
is formed at the cell area by performing a self aligned source etching process and injecting cell source/drain ions. Then, a LDD (Lightly Doped Drain) ion injection process, a spacer forming process, a peripheral circuit source/drain ions injection process and a thermal process are sequentially performed to form a transistor of a LDD structure. An inter-insulating film (not shown) is formed on the entire structure. A drain contact
37
is formed at the cell drain
36
by performing a contact process.
Meanwhile, as the programming of the flash memory cell is operated by injecting hot carriers in view of cell characteristic, the cell drain
36
where the hot carriers are occurring has an abrupt structure. So as to keep this structure, it is believed that the thermal process has to be performed after the cell source/drain ion injection process. However, according to the above-mentioned conventional method, the thermal process is performed after the cell source/drain ion injection process. At this time, if the thermal process is not performed after the peripheral circuit source/drain ion injection process to improve the cell characteristic, the junction of the peripheral circuit becomes an abrupt structure, thus the hot carrier reliability characteristic is deteriorated in view of transistor characteristic. In other words, in case that the flash memory is manufactured by the conventional method, there is a problem that the hot carrier reliability characteristic both of the cell area and the peripheral circuit area could not be satisfied.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to solve the problems involved in the prior art, and to provide a method of manufacturing a flash memory device capable of increasing the coupling ratio and also of improving reliability of hot carriers both at the peripheral circuit area and the cell area upon operation of the device, by which a control gate is formed to surround one side of a floating gate and the source/drain junction of the peripheral circuit area is formed before formation of the drain junction of the memory cell area.
To achieve the above object, the method of manufacturing a flash memory cell device is characterized in that it comprises the steps of forming a tunneling oxide film and a first ploysilicon layer on a semiconductor substrate and then patterning the first polysilicon layer by etching process using a floating gate as a mask; forming a cell source at an active region of a cell area through cell source ion injection; forming a dielectric film and a second polysilicon layer, and then pattering the second polysilicon layer while opening a portion of the first polysilicon layer pattern so that a gate electrode can be formed at a peripheral circuit area; performing sequentially a LDD ion injection process, a spacer forming process, a peripheral circuit source/drain ion injection process and a thermal process for activating ions to form a transistor of a LDD structure, wherein during the process of forming the spacer, a spacer is formed even at the side of the second polysilicon pattern on the cell area; etching the first and second polysilicon layer patterns at the cell area to form a floating gate and a control gate surrounding one side of the control gate through a self aligned etching process using the control gate and the spacer as masks; and forming a cell source line and a cell drain using the cell source self aligned etching process and the cell source/drain ion injection process.
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Kim Sang Soo
Lee Young Chun
Shin Jin
Hyundai Electronics Industries Co,. Ltd.
Niebling John F.
Pennie & Edmonds LLP
Whitmore Stacy
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