Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-06-22
2003-01-28
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S622000, C438S634000, C438S700000, C438S675000, C438S672000
Reexamination Certificate
active
06511908
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application is related to Japanese application No. 2000-193001 filed on Jun. 27, 2000, whose priority is claimed under 35 USC §119, the disclosure of which is incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing semiconductor devices. In particular it relates to a method of manufacturing semiconductor devices having a dual damascene structure wiring.
2. Description of Related Art
As a result of the recent scale down of wiring with the scale down of the semiconductor devices, the wiring resistance and wiring capacitance have increased so much that wiring delay represented by RC can not be neglected against the operating rate of LSI. Further, together with the scale down of wiring, the current density of the wiring has also increased, which gives rise its serious problems of fall of credibility of the wiring due to electromigration and rise of power consumption due to increase of the wiring capacitance.
So, copper, which is less resistant and shows higher electromigration tolerance than aluminum, has come into use as wiring material.
However, because the patterning of copper by a conventional dry etching technology is difficult, a damascene method using CMP method has been adapted. In particular, a dual damascene method, in which wiring trenches and contact holes are made simultaneously, has recently been developed.
Hereinafter a general dual damascene method will be explained.
At first, as shown in FIG.
2
(
a
), an interlayer insulating film
22
made of BPSG (boron-phosphorus-silicate glass) is formed on a semiconductor substrate
21
having a transistor (not shown) formed thereon. A contact hole is formed in this interlayer insulating film
22
. On the interlayer insulating film
22
including the contact hole, a tungsten film is formed and its surface is polished by a CMP method so that a tungsten plug
23
is buried in the contact hole.
Then, as shown in FIG.
2
(
b
), an etching stop film
24
is deposited and a non-fluorinated organic polymer film
25
having a dielectric constant of 3.0 is formed thereon. In this non-fluorinated organic polymer film
25
, a trench is formed for a damascene wiring structure, and copper is buried in the damascene wiring trench to form a first layer copper wiring
26
.
Subsequently, as shown in FIG.
2
(
c
), a copper diffusion inhibiting film
27
is formed by a plasma CVD method on the non-fluorinated organic polymer film
25
and the first layer copper wiring
26
, and thereon are formed a non-fluorinated organic polymer film
28
, a copper diffusion inhibiting film
29
, a non-fluorinated organic polymer film
30
and an etching stop film
31
. Then, a contact hole
33
for connecting the first copper wiring
26
and the second wiring is formed by dry etching using a resist mask
32
having a predetermined shape.
As shown in FIG.
2
(
d
), a wiring trench
35
is formed by dry etching using a resist mask
34
having a predetermined shape so as to include the contact hole
33
.
As shown in FIG.
2
(
e
), copper is buried in the contact hole
33
and the wiring trench
35
to form a copper dual damascene wiring
36
.
According to this dual damascene method, it is necessary to use the etching stop films in order to control the depth of the wiring trenches in dry etching for forming the wiring trenches in the interlayer insulating films because the depth of the trenches directly affects the wiring resistivity. Further, the copper diffusion inhibiting films are also needed for preventing copper from diffusing in the interlayer insulating films after forming the wiring because copper easily diffuses in the interlayer insulating film even by thermal treatment at low temperatures.
In general, a SiN film is used as an etching stop insulating film because it is easy to attain the selectivity in dry etching in comparison with insulating films such as silicon dioxide (SiO
2
) film or fluorinated silicon dioxide (FSG) film. Further, the SiN film is also used as the copper diffusion inhibiting film because of having the function of inhibiting the copper diffusion.
However, because the SiN film shows a high dielectric constant of not less than 7, it is difficult to lower the wiring capacitance effectively by using the SiN film generally formed in the above method even if it is used in combination with a film of a low dielectric material (e.g. film having a dielectric constant of not more than 3.0) as an interlayer insulating film in the multilayer wiring structure. Here, the wiring capacitance means the capacitance which is generated between wirings arranged in a vertical direction or in a horizontal direction.
On the other hand, it is possible for lowering the wiring capacitance not to use the SiN film which has been used as an etching stop film at the time of forming the dual damascene structure wiring. In this case, however, there brings about other problems that it is difficult to control the depth of the wiring trenches, and that the shape of the contact holes may vary widely depending upon uniformity within plane of dry etching, and as a result, that the resistivity of the dual damascene wiring structure becomes unstable.
Further, the use of a boron nitride (BN) film as an etching stop film is described, for example, in Japanese Patent Laid-open H7(1995)-283312. However, since only relatively higher dielectric constant of about 4 is attained by a conventional BN film forming process, for example, by a plasma CVD method using B
2
H
6
and N
2
as materials at temperature of about 350° C. in a 300 W plasma atmosphere, no sufficient fall in both the wiring capacitance in the vertical direction and in the horizontal direction is attained yet.
Moreover, the method of depositing the BN film as described above can provides only a deposition rate of 9 nm/min or less. That gives rise to problems such as prolonged manufacturing process and elevation of the manufacturing cost.
SUMMARY OF THE INVENTION
The present invention has been achieved in view of the above-described problems. An object of the present invention is to provide a method of manufacturing a semiconductor device which can realize a decreased wiring capacitance in the vertical direction and in the horizontal direction by forming an interlayer insulating film of low dielectric constant and realize high speed operation by a simple method.
According to the present invention, there is provided a method of manufacturing a semiconductor device comprising a wiring formation step including: forming an interlayer insulating film composed of a boron nitride film having a dielectric constant of less than 4 on an (n)-th layer wiring, forming a hole and/or a trench in the interlayer insulating film, burying the hole and/or trench with a conductive material and forming an (n+1)-th layer wiring on the hole and/or trench.
REFERENCES:
patent: 5272117 (1993-12-01), Roth et al.
patent: 5641974 (1997-06-01), den Boer et al.
patent: 6069069 (2000-05-01), Chooi et al.
patent: 6165891 (2000-12-01), Chooi et al.
patent: 6194321 (2001-02-01), Moore et al.
patent: 6376270 (2002-04-01), Gu et al.
patent: 7-283312 (1995-10-01), None
Kinoshita Takao
Orita Kunihiko
Duong Khanh
Jr. Carl Whitehead
Nixon & Vanderhye P.C.
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