Method of manufacturing a DRAM capacitor

Details Method of manufacturing a DRAM capacitor Method of manufacturing a DRAM capacitor

2000-04-17

2001-08-14

Chaudhuri, Olik (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S254000, C438S396000, C438S397000

Reexamination Certificate

active

06274427

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and more particularly, to a capacitor structure of a semiconductor device applicable to a storage capacitor of a semiconductor memory device, and a method of fabricating the same.
2. Description of the Prior Art
Storage capacitors are one of the main components of the memory cell of a semiconductor memory device.
In general, the output voltage from the memory cell is proportional to the capacitance value of the storage capacitor of the cell and thereof, the capacitor need to have a satisfactorily large capacitance value to ensure stable operation of the cell or to improve the operation reliability of the cell. On the other hand, the capacitor needs to be further miniaturized with the recent progressing miniaturization and integration of the cell. Thus, in recent years, there has been the strong need to develop new capacitor structures that make it possible to realize a satisfactorily large capacitance value even if the cell is further miniaturized. To meet this need, various capacitor structures have been developed and disclosed, one of which is shown in FIG.
1
.
FIG. 1
shows a part of the memory cells of a semiconductor memory device, in which prior-art storage capacitors
130
are formed on the surface of a semiconductor substrate
101
along with Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs)
131
. One of the MOSFETs
131
and a corresponding one of the capacitors
130
constitute the cell.
An isolation dielectric
102
is selectively formed on the surface of the substrate
101
, defining active areas (not shown) thereon. In each of the active areas, a gate insulator
120
is selectively formed on the surface of the substrate
101
, a gate electrode
103
is formed on the gate insulator
120
, and a pair of source/drain regions
121
a
and
121
b
are formed in the substrate
101
at each side of the gate electrode
103
. The pair of source/drain regions
121
a
and
121
b,
the gate insulator
120
, and the gate electrode
103
constitute the MOSFET
131
in each of the active areas.
A first interlayer dielectric layer
104
is formed to cover the isolation dielectric
102
, the gate electrodes
103
, and the pairs of exposed source/drain regions
121
a
and
121
b.
A second interlayer dielectric layer
105
is formed on the first interlayer dielectric layer
104
. The layer
105
is thicker than the first interlayer dielectric layer
104
, because a wiring layer
106
is formed in the layer
105
. The wiring layer
106
is electrically connected to the respective source/drain regions
121
a.
The wiring layer
106
does not appear in the cross-section of the device shown on FIG.
1
and thus, it is illustrated by broken lines.
A silicon nitride (SiN
x
) layer
107
is formed on the second interlayer dielectric layer
105
. The layer
107
serves as an etch stop layer in the process of etching the layers overlying the layer
107
.
Contact holes
122
are formed to penetrate the SiN
x
layer
107
and the second and first interlayer dielectric layers
105
and
104
. The holes
122
reach the corresponding source/drain regions
121
b,
exposing the same. The holes
122
are filled with conductive contact plugs
117
. The bottoms of the plugs
117
are contacted with and electrically connected to the corresponding source/drain regions
121
b.
Lower electrodes
116
, which serve a charge storage electrodes of the respective memory cells, are formed on the SiN
x
layer
107
to be overlapped with the respective active areas. These electrodes
116
are separated from each other by small gaps. As seen from
FIG. 1
, each of the electrodes
116
is formed by a circular-plate-shaped bottom.
116
a
and a cylindrical sidewall
116
b
connected to the periphery of the bottom
116
a.
The sidewall
116
b
extend upward from the periphery of the bottom
116
a.
The center of the bottom
116
a
is contacted with and electrically connected to the top of a corresponding one of the contact plugs
117
.
A capacitor dielectric
114
is formed to cover all the lower electrodes
116
. The dielectric
114
is contacted with not only the exposed areas of the electrodes
116
but also those of the silicon nitride layer
107
exposed from the gaps between the electrodes
116
. The dielectric
114
is commonly used for all the electrodes
116
.
An upper electrode
115
is formed on the capacitor dielectric
114
to be opposite to all the lower electrodes
116
. The electrode
115
is commonly used for all the electrodes
116
. The electrode
115
extends along the dielectric
114
.
The upper electrode
115
, the capacitor dielectric
114
, and one of the lower electrodes
116
constitute each of the storage capacitors
130
. Each of the MOSFETs
131
and a corresponding one of the capacitors
130
constitute the memory cell.
Next, a method of fabricating the prior-art semiconductor memory device shown in
FIG. 1
is explained below with reference to
FIGS. 2A
to
2
H.
First, as shown in
FIG. 2A
, the isolation dielectric
102
, which is made of silicon dioxide (SiO
2
), is selectively formed on the surface of the semiconductor substrate
101
, thereby defining the active areas. Next, a SiO
2
layer (not shown) is formed on the whole surface of the substrate
101
and an impurity-doped polysilicon layer (not shown) is deposited on the SiO
2
layer thus formed. The SiO
2
and polysilicon layers are patterned to have a specific shape, thereby forming the gate insulators
120
and the gate electrodes
103
on the surface of the substrate
101
in the respective active areas.
Using the isolation dielectric
102
and the gate electrodes
102
as a mask, an impurity is selectively implanted into the substrate
101
, thereby forming the pairs of the source/drain regions
121
a
and
121
b
in the respective active areas. Each pair of source/drain regions
121
a
and
121
b
is located in self-alignment with respect to a corresponding one of the gate electrodes
103
.
Thus, the MOSFETs
131
are fabricated on the substrate
101
, each which is formed by one of the pairs of source/drain regions
121
a
and
121
b,
a corresponding one of the gate insulators
120
, and a corresponding one of the gate electrodes
103
.
Subsequently, the first interlayer dielectric layer
104
, which is made of SiO
2
, is formed to cover the whole surface of the substrate
101
. At this time, the isolation dielectric
102
and the MOSFETs
131
are covered with the layer
104
, Then, the second interlayer dielectric layer
105
, which is made of BoroPhospoSilicate Glass (BPSG), is formed on the first interlayer dielectric layer
104
. The layer
105
contains in its inside the wiring layer
106
electrically connected to the respective source/drain regions
121
a.
The SiN
x
layer
107
is formed on the second interlayer dielectric layer
105
thus formed by a Chemical Vapor Deposition (CVD) method.
On the SiN
x
layer
107
thus formed, a patterned resist film
109
having openings
109
a
is formed. The openings
109
a
are used for forming the contact holes
122
and located at positions right over the respective source/drain regions
121
b.
The state at this stage is shown in FIG.
2
A.
Following this step, using the patterned resist film
109
as a mask, the SiN
x
layer
107
and the second and first interlayer dielectric layers
105
and
104
are etched selectively and successively. Thus, as shown in
FIG. 2B
, the contact holes
122
are formed to penetrate the layers
107
,
105
, and
104
, exposing the underlying source/drain regions
121
b.
Thereafter, the resist film
109
is removed.
A first conductive layer (not shown) having a thickness large enough for filling the contact holes
122
is formed on the SiN
x
layer
107
. As the first conductive layer, for example, an impurity-doped (i.e., n- or p-type) polysilicon layer is used. The first conductive layer thus formed is then etched back until the underlying SiN
x
layer
107
is exposed, thereby leaving selectively the first co

Affiliated with

Also associated with

Rating

Method of manufacturing a DRAM capacitor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of manufacturing a DRAM capacitor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a DRAM capacitor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2478330