Method of manufacturing a DRAM and logic device

Details Method of manufacturing a DRAM and logic device Method of manufacturing a DRAM and logic device

2000-04-04

2001-04-17

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S656000

Reexamination Certificate

active

06218235

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to methods of manufacturing semiconductor devices and, more specifically, to a method of manufacturing a semiconductor device in which a memory device formed by a self alignment contact process and a logic device formed by a salicide process (such a semiconductor device is hereinafter referred to as “a mixed device”) are arranged on the same semiconductor substrate.
2. Description of the Background Art
Recently, semiconductor devices are required to be smaller and highly integrated. Among memory devices such as DRAMs (Dynamic Random Access Memories), for example, there is a device which can even store information of 1 Gigabit in one chip.
Multimedia development requires that the semiconductor devices are smaller and light weighted while having complicated functions. To satisfy all of the above mentioned requirements, the latest semiconductor devices must be provided with various devices in one chip. The most typical example is that memory and logic devices are formed on the same semiconductor substrate in one chip.
Conventionally, various microminiaturization pattern forming techniques have been developed for memory devices such as DRAMs. Among these techniques, there is a self alignment contact (hereinafter abbreviated as “SAC”) technique. Generally, an alignment error of masks is taken into account a process of forming a contact hole. For example, an opening pattern of a mask for a gate electrode and that for a contact hole in a source/drain region are designed to allow for a margin in alignment. However, as SAC does not require consideration of alignment tolerance for the opening pattern of the mask, it is considered a significant technique for forming a memory device.
Now, referring to
FIGS. 58A
to
66
A as well as
FIGS. 58B
to
66
B, a conventional SAC process for a DRAM device will be described.
FIGS. 58A
to
66
A show memory cell regions, whereas
FIGS. 58B
to
66
B show peripheral circuit regions or the like which are outside the memory cell regions. In the conventional SAC process of the DRAM device, first, as shown in
FIGS. 58A and 58B
, an isolation oxide film
102
is formed by trench isolation in well regions
101
a
and
101
b
in a semiconductor substrate. A gate insulating film
103
is formed by thermal oxidation or the like in a device formation region which has been separatedly formed by isolation oxide film
102
. Then, a gate electrode
104
and an insulating film
105
including a silicon nitride film are formed by using the same mask. A source/drain region
106
a
is formed in a p well region
101
a
by implanting n type impurities by means of ion implantation or the like. In addition, a source/drain region
106
b
is formed in an n well region
101
b
by implantation of p type impurities.
Thereafter, as shown in
FIGS. 59A and 59B
, a silicon oxide film
107
and silicon nitride film
108
are sequentially formed to cover a main surface of the semiconductor substrate. In forming silicon oxide film
107
, any of CVD (Chemical Vapor Deposition) and oxidation may be used.
As shown in
FIGS. 60A and 60B
, a resist film is formed on silicon nitride film
108
. Thereafter, the resist film is subjected to photolithography for forming an n type transistor region other than in the memory cell region. Then, the resist film in the n type transistor region other than in the memory cell region is etched. A resist film
109
is formed in the n type transistor region in the memory cell region and in the p type transistor region other than in the memory cell region. Then, silicon nitride film
107
, silicon oxide film
108
and gate insulating film
103
are subjected to anisotropic etching using resist film
109
as a mask. A sidewall nitride film
108
a
of a transistor is thereby formed. Then, n type impurities are further implanted to the n type transistor region in the memory cell region using insulating film
105
and sidewall nitride film
108
a
as masks, so that source/drain region
106
a
comes to have an LDD (Lightly Doped Drain) structure.
Then, a resist film is formed to cover an entire surface of the semiconductor substrate. The resist film is subjected to photolithography for forming a p type transistor region other than in the memory cell region. The resist film in the p type transistor region other than in the memory cell region is etched. Thus, a resist film
110
is formed. Silicon nitride film
108
is subjected to anisotropic etching using resist film
110
as a mask, so that a sidewall nitride film
108
b
is formed. Then, the p type impurities are further implanted to the n type transistor region using insulating film
105
and sidewall nitride film
108
b
as masks in the p type transistor region, so that source/drain region
106
b
comes to have the LDD structure. As a result, the structure as shown in
FIGS. 61A and 61B
is obtained. Here, the conductivity type of the well region and that of impurities to be implanted are not limited to the above mentioned conductivity type, and mutually opposite conductivity types may be employed. Then, resist film
110
is removed.
As shown in
FIGS. 62A and 62B
, a silicon oxide film including boron and phosphorus, that is, a BPSG (Boro Phospho Silicate Grass) film
111
is formed to cover the entire surface of the semiconductor substrate. Thereafter, the surface of BPSG film
111
is subjected to a thermal treatment or a planarization process such as CMP (Chemical Mechanical Polishing). A silicon oxide film
112
is formed on BPSG film
111
.
Successively, a resist film is formed on silicon oxide film
112
. As shown in
FIGS. 63A and 63B
, a resist film
113
is formed in a pattern for forming a self alignment contact opening between gate electrodes in the memory cell region.
Referring to
FIGS. 64A and 64B
, silicon oxide film
112
and BPSG film
111
are subjected to anisotropic etching using resist film
113
as a mask and silicon nitride film
108
as an etching stopper in the memory cell region. As shown in
FIGS. 65A and 65B
, resist film
113
is removed.
Now, referring to
FIGS. 66A and 66B
, silicon nitride film
108
and silicon oxide film
107
are sequentially subjected to anisotropic etching using silicon oxide film
112
and BPSG film
111
as masks. Thus, a self alignment contact hole
114
is formed. A conductive material (not shown) for forming an interconnection layer for a bit line or the like is buried in self alignment contact hole
114
. As a result, source/drain region
106
a
formed in the semiconductor substrate and other conductive layers are electrically connected.
On the other hand, in the logic device formation region, to simultaneously reduce a parasitic resistance of the source/drain region and an interconnection resistance of the gate electrode, a technique referred to as salicide (Salicide: Self-aligned Silicide) for forming selectively and in a self-aligning manner a refractory metal silicide film on the surface of the gate electrode in the source/drain region. Referring to
FIGS. 67
to
72
, the salicide process will be described.
A method of manufacturing the structure shown in
FIG. 67
is performed in a similar manner as that of forming the region other than the memory cell region shown in
FIGS. 58B
to
61
B.
As shown in
FIG. 68
, a silicon oxide film
115
including a salicide protection film is formed to cover the entire surface of the semiconductor substrate. Then, a resist film is formed to cover the entire surface of the semiconductor substrate. Photolithography is performed such that the resist film is left only in the portion where silicon oxide film
115
is to be left. By etching the resist film not in the portion where silicon oxide film
115
is to be left, a resist film
116
is formed as shown in FIG.
69
. Silicon oxide film
115
is subjected to anisotropic etching using resist film
116
as a mask. Resist film
116
is removed. This results in the structure shown in FIG.
70
. Successively, referring to
FIG. 71
, a refractory metal silicide film
117
such

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