Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-02-07
2002-04-23
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S255000, C438S254000, C438S396000, C438S398000
Reexamination Certificate
active
06376303
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a capacitor and to a method of fabricating semiconductor devices comprising the same. More particularly, the present invention relates to a method of manufacturing a capacitor having a high storage capacitance and to a method of fabricating a semiconductor device comprising the same.
2. Description of the Prior Art
Recently, due to a rapidly increasing and widespread usage of computers, the need for semiconductor devices is expanding. Semiconductor devices having a high storage capacitance and a faster operating speed are now in great demand. To this end, current technology is focused on developing and realizing memory devices having a high degree of integration, response speed, and reliability.
Currently, a dynamic random access memory (DRAM) device which has a high memory capacity and random open input/output functions is widely used as a semiconductor memory device. DRAM devices generally comprise a memory cell region, at which information data is stored in the form of electric charge, and a peripheral circuit for the input/output of data to and from the memory cell region. Furthermore, DRAM devices conventionally include at least one access transistor and a storage capacitor.
Such a storage capacitor must be made smaller and smaller to meet the demand for memory devices having an increasingly higher degree of integration. Accordingly, manufacturing a capacitor having a higher storage capacitance and reduced size is increasingly becoming a challenge. In fact, producing a capacitor having a markedly increased storage capacitance within the same amount of area occupied on a substrate surface by any current storage capacitor is an ever prevailing task.
Generally, capacitance C is represented by the following mathematical expression.
C=&egr;
0
&egr;A/d
In the above expression, &egr;
0
and &egr; respectively represent the dielectric constant in a vacuum and a dielectric constant of a dielectric film of a capacitor, while A represents the effective area and d represents the thickness of a dielectric film.
Referring to the above mathematical expression, storage capacitance can be increased by forming the dielectric film from a material having a higher dielectric constant, increasing the effective area of the capacitor, or by decreasing the thickness of the dielectric film.
However, the thickness of a dielectric film can be minimized only to a certain extent in highly integrated memory devices. Furthermore, although a number of dielectric materials having a high dielectric constant and processes of forming a dielectric film utilizing these materials are widely known in the art, processes of forming dielectric films of a material other than a nitride are difficult to incorporate into a mass production method of manufacturing semiconductor devices.
In view of the above, i.e., with respect to the method of manufacturing semiconductor devices, it is easiest to maximize the storage capacitance of a capacitor by maximizing its effective area. For instance, U.S. Pat. No. 5,185,282 discloses a stacked capacitor having the shape of a cup or cylinder, while U.S. Pat. No. 5,656,536 discloses a crown-shaped stacked capacitor, and U.S. Pat. Nos. 5,716,884 and 5,807,782 disclose fin-shaped stacked capacitors.
On the other hand, U.S. Pat. No. 5,877,052 discloses a method of increasing the storage capacitance by forming silicon hemispherical grains (HSG) on a storage electrode. Further, U.S. Pat. No. 5,913,119 discloses a method of forming an HSG layer on a cylindrical storage electrode by combining the above-mentioned techniques.
FIGS. 1A
to
1
D are sectional views illustrating a method of fabricating a capacitor having a cylindrical storage electrode formed with a silicon HSG layer according to U.S. Pat. No. 5,913,119.
As shown in
FIG. 1A
, a field oxide layer
3
is formed on a semiconductor substrate
1
for isolating various devices on the substrate
1
. A gate oxide layer
5
is formed by thermal oxidation of the active region defined by the field oxide layer
3
. Then, a poly-silicon layer
7
and subsequently a silicon oxide layer
9
are formed on the gate oxide layer
5
. These layers are then patterned by a photolithography process to thereby yield a gate electrode
11
.
Next, an oxide layer is deposited on the surface of substrate
1
adjacent gate electrode
11
, and spacers
13
are produced on the side walls of the gate electrode
11
by etching the oxide layer. This process is followed by an ion doping process to form a transistor source/drain region
15
.
An insulating interlayer
17
and then a silicon nitride layer
19
are then formed over the substrate
1
. Selected portions of the insulating interlayer
17
and silicon nitride layer
19
are then etched to produce a contact hole which exposes the source/drain region
15
.
A polysilicon layer is deposited on the silicon nitride layer
19
so as to fill the contact hole. A polysilicon contact
21
is then formed in the contact hole by performing an etch back process.
Next, a cylindrical storage electrode is produced. First, a silicon oxide layer is deposited on the silicon nitride layer
19
and contact
21
. Then, utilizing a photolithography process in which a photoresist pattern
27
serves as a mask, the silicon oxide layer is etched to form a silicon oxide layer pattern
23
.
As shown in
FIG. 1B
, after the photoresist pattern
27
is removed, amorphous silicon layers
29
,
31
,
33
, and
35
each having different doped levels of impurities are sequentially formed on silicon nitride layer
19
, contact
21
, and silicon oxide layer pattern
23
. The upper portions of amorphous silicon layers
29
,
31
,
33
, and
35
are then polished by a chemical mechanical polishing (CMP) process. The silicon oxide layer pattern
23
is etched away to yield a cylindrical storage electrode
36
.
Referring to
FIG. 1C
, silicon HSG seeds are deposited on the cylindrical storage electrode
36
. Then the seeded storage electrode is subjected to a number of heat treatment processes to grow the seeds and convert amorphous silicon layers
29
,
31
, and
33
into a silicon HSG layer
37
on the surface of the storage electrode
36
.
Referring to
FIG. 1D
, a dielectric film
39
having an ONO (oxidized-silicon nitride-silicon oxide) structure is formed on the silicon HSG layer
37
. Thereafter, a polysilicon plate electrode
41
is formed on the dielectric film
39
. An etching process shapes the resultant structure to produce a capacitor
43
comprising storage electrode
36
, dielectric film
39
, and plate electrode
41
.
However, because the above-described process of manufacturing a capacitor attempts to increase the effective area by varying the cylindrical or crown-shaped structural configuration of the capacitor, rather than increasing the surface area of the storage electrode itself, the process faces a fundamental limitation in increasing the storage capacitance. Furthermore, a significant increase in capacitance can hardly be expected compared to the many other variations of cylindrical capacitors known in the art.
Nonetheless some increase in the effective area of the capacitor can be expected by forming a silicon HSG layer on the surface of the storage electrode according to the disclosed method. However, the method is complex, involving the depositing of a number of amorphous silicon layers and a number of heat treatment processes. Accordingly, the prior art method is disadvantageous in that it has low reproducibility and hence, it is associated with high manufacturing costs.
In view of these problems, other methods of forming a storage electrode of a high capacitance capacitor have been developed. One of these methods is as disclosed in U.S. Pat. No. 5,843,822. This patent discloses the use of thermal chemical vapor deposition (thermal CVD) and plasma enhanced chemical vapor deposition (PECVD) to form oxide layers exhibiting a different etching rate from each other when etched by hydrofluoric acid (HF)
Lim Jeon Sig
Seo Tae Wook
Bowers Charles
Chen Jack
Volentine & Francos, PLLC
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