Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-07-22
2001-05-22
Lee, Eddie C. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S253000, C438S255000, C438S398000
Reexamination Certificate
active
06236080
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a process for manufacturing semiconductor DRAM cells, and more specifically, to a method for forming a capacitor with a crown shaped structure and a plurality of vertical fins.
BACKGROUND OF THE INVENTION
Semiconductor Dynamic Random Access Memory (DRAM) devices have been applied widely in the integrated circuits with the advance of semiconductor manufacture. Typically, a memory cell consists of a storage capacitor and an access transistor for each bit to be stored by the semiconductor DRAM. Either the source or drain of the transistor is connected to one terminal of the capacitor. The other side of the transistor and the transistor gate electrode are connected to external connection lines called the bit line and the word line, respectively. The other terminal of the capacitor is connected to a reference voltage. Thus, the formation of a DRAM memory cell comprises the formation of a transistor, a capacitor and contacts to external circuits.
However, with the coming of Ultra Large Scale Integrated (ULSI) DRAM devices, the sizes of memory cells have gotten smaller and smaller such that the area available for a single memory cell has become very small. This has caused a reduction in capacitor area, which in turn results in a reduction in cell capacitance. Namely, the amount of the charge capable of being stored by the capacitor decreases. Besides, for very small memory cells, planar capacitors produced have lower reliability in operation. Accordingly, the important issue currently is how to promote the capacitance and reliability of capacitors with the decreasing scale of the devices and the increasing integration of the integrated circuits.
For resolving the above problems, the manufacture of capacitors tends to increase the surface area of the storage electrode, and results in the development of the various types of capacitors such as the trench capacitor and the stacked capacitor. Except the high dielectric films are used for the capacitor, the bottom electrodes such as the crown shaped structure, the fin shaped structure, the spread shaped structure and cylinder shaped structure are also used to increase the storage efficiency for the capacitors manufactured in the limited areas. However, the capacitances of those stack structures can still hardly to provide enough storage spaces for satisfying the capacitance required for 256M or 1 G DRAM within the limited design rule. Especially, as described above, with the integration of the semiconductor devices increasing, the areas which the various devices occupied become smaller and smaller, and the scales of the devices are sustained shrinking. Thus, the required fin shaped structures and the spread shaped structures can not be defined effectively and successfully in the limited areas by using the conventional technique due to the restriction of the microlithography. Therefore, the yield and storage capacitance of the capacitors manufactured by the prior technique and process can not promoted effectively when the areas that the devices occupied still shrunk.
SUMMARY OF THE INVENTION
The prime objective of the present invention is to provide a method for manufacturing the integrated circuit capacitor with an increasing bottom electrode surface area.
The second objective of the present invention is to provide a method for manufacturing the DRAM cell with the crown shaped electrode which comprises of a plurality of arch structures for increasing the surface areas.
The another objective of the present invention is to form the capacitor with a plurality of fin shaped structures defined by using the plurality of discrete rugged polysilicon grains.
A method for manufacturing an integrated circuit capacitor is provided in the present invention. First, an oxide layer and a nitride layer are formed on a semiconductor substrate in sequence. An etching step is performed to etch the nitride layer and the oxide layer for defining a contact hole on the semiconductor substrate. A conducting plug is then formed into the contact hole. Next, a dielectric layer is formed on the nitride layer and the conducting plug. The dielectric layer is etched to form an opening for exposing the top surfaces of the conducting plug and a portion of the nitride layer. A plurality of discrete rugged polysilicon grains are formed on the exposed surfaces of the dielectric layer, the conducting plug and the nitride layer. The dielectric layer is next etched to form a plurality of cavities on the top surface of the dielectric layer by using the plurality of discrete rugged polysilicon grains as an etching mask. A first conducting layer is formed on the surfaces of the plurality of discrete rugged polysilicon grains, the dielectric layer, the nitride layer and the conducting plug, and filling into the plurality of cavities to form a plurality of vertical fins. Then, the plurality of discrete rugged polysilicon grains and the first conducting layer are etched to define a bottom electrode. After removing the dielectric layer, a capacitor dielectric film is formed on the outer surfaces of the first conducting layer, the plurality of discrete rugged polysilicon grains and the nitride layer. A second conducting layer is deposited on the outer surface of the capacitor dielectric film to serve as a top electrode.
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Diaz José R
Lee Eddie C.
Worldwide Semiconductor Manufacturing Corp.
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