Method of manufacture of memory device with high coupling ratio

Details Method of manufacture of memory device with high coupling ratio Method of manufacture of memory device with high coupling ratio

1997-09-29

1999-07-13

Thomas, Tom

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438260, 438261, H01L 218246, H01L 218247

Patent

active

059239743

ABSTRACT:
A method of forming a semiconductor memory device with a variable thickness gate oxide layer including a tunnel oxide layer and a thicker gate oxide layer includes the following steps. Provide a doped silicon semiconductor substrate coated with a tunnel oxide layer, a first floating gate conductor layer and a dielectric layer. Form a mask with an gate oxide opening through the mask. Etch through the gate oxide opening to form a gate oxide trench through the first polysilicon layer, the dielectric layer and the tunnel oxide layer down to the substrate. Form a gate oxide layer at the base of the gate oxide trench. Deposit a second floating gate conductor layer over the device on the exposed surfaces of the dielectric layer and down into the gate oxide trench including the gate oxide layer. Form a thin interelectrode dielectric layer upon the floating gate conductor layer. Deposit a control gate conductor layer over the device covering the device. Pattern the control gate conductor layer, the thin interelectrode dielectric layer, and the floating gate conductor layer down to the tunnel oxide layer. Form self-aligned source/drain regions in the substrate by a LATI method.

REFERENCES:
patent: 5554544 (1996-09-01), Hsu
patent: 5556799 (1996-09-01), Hong
patent: 5796140 (1998-08-01), Tomioka
Yosiaki S. Hisamune et al. "A High Capacitive Coupling Ratio (HiCR) Cell for 3V Only 64 Mbit and Future Flash Memories" (1993) IEDM, pp. 93-19-93-22.

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