Method of manufacture of a silicon carbide MOSFET including...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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Details

C438S285000, C438S518000, C438S519000

Reexamination Certificate

active

07029969

ABSTRACT:
A semiconductor device and its manufacturing method in which the trade-off relationship between channel resistance and JFET resistance is improved. The same mask is used to form a source region and a base region by ion implantation. In a vertical MOSFET including SiC, a source region and a base region are formed by ion implantation using the same tapered mask to give the base region a tapered shape. The taper angle of the tapered mask is set to 30° to 60° when the material of the tapered mask has the same range as SiC in ion implantation, and to 20° to 45° when the material of the tapered mask is SiO2.

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patent: 2004/0106262 (2004-06-01), Theiss et al.
patent: 2004/0188755 (2004-09-01), Tarui et al.
patent: 11-111728 (1999-04-01), None
patent: 11-274173 (1999-10-01), None

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