Method of manufacture of a semiconductor integrated circuit...

Details Method of manufacture of a semiconductor integrated circuit... Method of manufacture of a semiconductor integrated circuit...

2007-12-11

2007-12-11

Le, Thao X (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S197000, C438S268000, C438S622000, C257SE27098, C257SE21661

Reexamination Certificate

active

11651095

ABSTRACT:
For improving the filing properties between vertical MISFETs constituting a SRAM memory cell, the vertical MISFETs are formed over horizontal drive MISFETs and transfer MISFETs, and they are disposed with a narrow pitch in the Y direction and a wide pitch in the X direction. After a first insulating film (O3-TEOS) having good coverage is disposed over columnar laminates having a lower semiconductor layer, an intermediate semiconductor layer, an upper semiconductor layer and a silicon nitride film and a gate electrode formed over the side walls of the laminates via a gate insulating film to completely fill a narrow pitch space, a second insulating film (HDP silicon oxide film) is deposited over the first insulating film, resulting in an improvement in the filling properties, even in a narrow pitch portion, between vertical MISFETs having a high aspect ratio.

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Watanabe, et al., “A Novel Circuit Technology with Surrounding Gate Transistors (SGT's) for Ultra High Density DRAM's”, IEEE Journal of Solid-State Circuits, vol. 30, No. 9, Sep. 1995.

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