Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1990-09-18
2004-06-22
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S940000
Reexamination Certificate
active
06753253
ABSTRACT:
FIRST ASPECT OF THE PRESENT INVENTION
The present invention, in one aspect thereof, relates to techniques for manufacturing and testing a semiconductor integrated circuit device, and more particularly to techniques which are effective for enhancing a productivity in the development of a large-scale logic integrated circuit device.
In the developments of, for example, a general purpose electronic computer system and a large-scale logic integrated circuit device for use in the system, it is actually difficult to fabricate the large-scale logic integrated circuit device having errorless perfect logical functions at the stage which precedes the assemblage of the circuit device into the system. Further, the corrections of the logical functions of the circuit device become indispensable due to the alteration of the specification of the system, or the like.
Therefore, the following methods are considered for coping with the logical defects of the large-scale logic integrated circuit device found out after the assemblage of the actual system and the corrections of the logical functions requested on the basis of the specification alteration or the like:
The request for the corrections of the logical functions is coped with by changing a mask pattern relative to wiring in accordance with a so-called master slice system wherein a large-scale logic integrated circuit device having desired logical functions is obtained merely by adding the design of the wiring among basic cells to a semiconductor wafer in the state in which the formation of the basic cells has been completed.
Besides, a test after the logic corrections is usually conducted for the large-scale logic integrated circuit device held in the wafer state, by the use of a so-called wafer prober.
By the way, techniques for manufacturing the large-scale logic integrated circuit device in accordance with the master slice system are contained in “LSI HANDBOOK”, p. 204-p. 205, edited by the Japan Society of Electronics and Communications, issued on Nov. 30, 1984 by the Ohm-Sha, Ltd.
Also, techniques for testing the semiconductor integrated circuit device in a chip state with the wafer prober are contained in the official gazette of Japanese Patent Application Laid-Open No. 116144/1985.
Second Aspect of the Present Invention
As a second aspect of the present invention, this aspect relates to a cutting depth controlling technique used in applying a cutting work to an LSI on a mask for exposure, using a focused ion beam or the like.
This second aspect of the present invention also relates to a cutting technique of a high accuracy which is carried out under radiation of an ion beam, and particularly to a technique of cutting with a high accuracy an internal layer of, for example, an LSI having a multilayer structure.
This second aspect of the present invention further relates to a semiconductor device and a cutting technique using an ion beam for making same, and particularly to a technique effective in its application to cutting and exposure of wiring using an ion beam to effect logical correction in a logical element, take measures against a defective design or make analysis of a defect.
Further, this second aspect of the present invention relates to a semiconductor integrated circuit device and particularly to a technique effective in its application to the analysis of defects.
Further, this second aspect of the present invention relates to a cutting depth monitoring technique in cutting an LSI or a mask for exposure using a focused ion beam or the like.
In an LSI developing process it has recently become very important to make debugging, correction or analysis of a defect by cutting or connecting a part of a wiring in an LSI chip To this end, there have heretofore been reported examples of cutting a wiring in an LSI chip using a focused ion beam.
For example, Japanese Patent Laid-Open No. 106750/83 (Focused Ion Beam Cutting Method) describes that it is possible to effect cutting at different etching depths by changing the dose amount, radiation time and acceleration voltage of an ion beam.
Further, as a technique associated with a higher integration of a semiconductor device such as an LSI (large scale integrated circuit) and shortening of the developing period, a technique of cutting a wiring of the LSI by radiating a focused ion beam to a predetermined cutting region with a view to making debugging, correction or analysis of a defect of the LSI is disclosed in detail, for example, in the foregoing Japanese Patent Laid-Open No. 106750/83, which technique is outlined as follows. In etching a workpiece selectively by radiating a focused ion beam thereto, desired etching depths for the workpiece are preset as positional functions and on the basis of the preset data the ion beam is radiated while changing the dose amount and radiation time of the beam as well as acceleration voltage, whereby it is intended to effect etching at different depths. The above patent publication fully describes an etching control in the depth direction, but as to positioning of the cutting region in the planar direction, the said publication merely states that an ion beam is radiated to a part to be cut while referring to a positioning mark formed on the workpiece.
Further, as a cutting technique using an ion beam in the production of a semiconductor device, there is known the technique disclosed in Japanese Patent Laid-Open No. 202038/83. According to an outline of this technique, there is provided an end point detecting means for detecting a cutting end point accurately by observing charged particles such as secondary ions or secondary electrons or an emission spectrum emitted from an ion beam-radiated part of a workpiece during cutting, whereby in removing a black spot defect caused by the adhesion of a light shielding film such as a chromium film to a part which should be transparent, for example, in a photo mask, it is intended to prevent a glass substrate located below the black spot defect from being damaged by excess cutting.
Further, according to a conventional technique for measuring the potential of a defective part of an internal circuit in the analysis of a defect of an IC (integrated circuit) or an LSI, a laser beam is applied to an insulation film on an aluminum wiring of the defective part to form a hole and probes are manually put on the surface of the wiring (e.g., Japanese Patent Publication No. 6173/79).
Third Aspect of the Present Invention
The present invention, in a third aspect thereof, relates to a technique which may be effectively applied to a semiconductor integrated circuit device having a multilayer wiring structure and a process for producing such a semiconductor integrated circuit device.
Recently, it has been increasingly important to develop an effective technique of repairing a defective part in an LSI (Large Scale Integrated Circuit) or changing a logical design thereof by disconnecting and properly reconnecting part of the wirings within the LSI circuit after the completion of the LSI which is still in the form of a wafer or chip.
To attain the above-described object, proposed in Japanese Patent Application No. 70979/1986 was a method of connecting wirings in an LSI by a combination of an ion beam technique and a laser CVD technique. According to the proposed method, after the completion of an LSI having, for example, a double-layer wiring structure, wirings in a first-level layer are interconnected for the purpose, for example, of repairing a defective part or changing a logical design. In this case, since the wiring in the uppermost layer is generally widely laid out in order to supply a power supply current, it is necessary to provide contact holes extending through the wiring in the uppermost-level layer so as to reach the wirings in the lower-level layers and also provide a connecting wiring through the contact holes. For this arrangement, an insulating film on the uppermost-level wiring layer, the second-level wiring layer and an intermediate insulating film between the second-level wiring layer and the first-level wi
Haraichi Satoshi
Hongo Mikio
Itoh Fumikazu
Shimase Akira
Takahashi Takahiko
Antonelli Terry Stout & Kraus
Chaudhari Chandra
Hitachi , Ltd.
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