Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2000-08-28
2002-02-12
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S264000, C438S595000
Reexamination Certificate
active
06346467
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of manufacturing a MOS transistor and a memory cell on a common semiconductor substrate and the device obtained thereby. The present invention has particular utility in manufacturing high-density integration semiconductor memory devices, such as flash electrically erasable programmable read only memories (flash EEPROMS), with design rules of about 0.18 micron and under.
BACKGROUND OF THE INVENTION
The flash EEPROM is so named because the contents of all of the memory's array cells can be erased simultaneously at high speed. Flash EEPROMs, unlike floating gate EEPROMs which include a separate select transistor in each cell to provide for individual byte erasure, eliminate the select transistor and provide bulk erasure. As a consequence, flash EEPROM cells can be made much smaller than floating gate EEPROM cells fabricated under the same design rules, thus permitting formation of high density memories having easy erasability and reprogrammability.
Conventional flash EEPROMs typically comprise a floating gate memory cell, which includes a source region, a drain region, and a channel region formed in a semiconductor substrate, usually a silicon wafer, and a floating gate formed above the substrate and located between the channel region and a control gate. Most flash EEPROM cells use a “double-poly” structure, wherein an upper layer formed of e.g., polysilicon and termed “poly 2”, forms the control gate and a lower layer of polysilicon, termed “poly 1”, forms the floating gate. The gate oxide layer is typically about 10 nm thick and the interpoly dielectric typically comprises a three layer composite of silicon oxide/silicon nitride/silicon oxide layers (“ONO”) of total thickness of about 25 nm or less.
In operation, to program the memory cell, typically by Channel Hot Electron (“CHE”) injection, a high voltage, such as about 10 volts, is applied to the control gate and a moderately high voltage, e.g. about 5 volts, is applied to the drain terminal while the source and substrate terminals are at ground potential. To erase the cell, either a Source Edge Erase (“SEE”) or a Channel Erase (“CE”) procedure can be utilized. According to the SEE procedure, a high negative voltage, such as −10 volts, is applied to the control gate and a moderately high voltage, e.g., about 5 volts, is applied to the source terminal while the drain potential floats. According to the CE procedure, a high negative voltage, such as −10 volts, is applied to the control gate and a moderately high voltage, e.g., about 7 volts, is applied to the device body (e.g., a well) while the source and drain potentials float. In either instance, a sufficiently large electric field is developed across the tunnel oxide and electrons can tunnel out from the floating gate either at the source terminal (SEE procedure) or through the channel region (CE procedure).
Flash EEPROM systems conventionally comprise a two-dimensional array of floating gate memory cells such as described above. The array typically includes several strings of floating gate memory transistors, each transistor being coupled to the neighboring transistor in the string by coupling the source of one device to the drain of the neighboring device, thereby forming bit lines. A plurality of word lines, perpendicular to the strings, each connect to the control gate of one memory cell of each string.
A CMOS transistor, referred to as a “row selector”, is employed at one end of each word line to supply program voltage on demand to each of the word lines. The row selecting transistor and other transistors, e.g., for power supply purposes, are formed in the semiconductor wafer substrate concurrent with the formation of the memory cell array and typically employ much of the same processing steps and conditions. In some instances, the transistor, termed a “poly 2 periphery transistor” is formed on a peripheral portion of the semiconductor substrate and utilizes the “poly 2”, or upper polysilicon layer used to form the control gates of the memory array cells.
In order to electrically contact the “poly 2” layer forming the gate electrode of such peripheral transistors and the control gate electrode of the memory array cells, a layer of a refractory metal, e.g., titanium (Ti) or tungsten (W), is typically formed over the “poly 2” electrode (with or without interposition of adhesion and/or barrier layer(s)) and suitably patterned and annealed. The use of tungsten for forming such contacts is particularly attractive because tungsten-based polysilicon gate electrode contacts can be formed with sub-micron sized dimensions (D. Hisamoto et al., 1995 Symposium on VLSI Technology Digest of Technical Papers, pp 115-116), and with very low sheet resistance (i.e., 1.6-3&OHgr;/□) when either a titanium nitride (TiN) or tungsten nitride (WN
x
) interlayer is provided between the tungsten layer and the polysilicon gate electrode layer (D. H. Lee et al., 1995 Symposium on VLSI Technology Digest of Technical Papers, pp 119-120; K. Kasai et al., IEDM 94, pp 497-500). However, a significant problem encountered with the use of tungsten as a gate electrode contact metal in memory array manufacture is oxidation thereof during high temperature (e.g., about 900° C.) furnace processing under an oxidizing ambient during MOS transistor and flash memory cell fabrication.
Thus, there exists a need for a process scheme, compatible with existing flash memory semiconductor manufacture, which allows formation of very low sheet resistance tungsten gate electrode contacts of deep submicron dimensions while reducing or eliminating oxidation thereof during subsequent processing.
DISCLOSURE OF THE INVENTION
An advantage of the present invention is a method of manufacturing a high-density flash memory array with an improved control gate electrode contact structure.
Another advantage of the present invention is a method of manufacturing a flash memory array including a control gate electrode structure which is resistant to oxidation during high temperature processing in an oxidizing ambient.
Still another advantage of the present invention is a method of simultaneously forming oxidation resistant tungsten-based contacts to the gate electrode of a MOS transistor and the control gate electrode of a memory cell of a flash EEPROM.
A still further advantage of the present invention is provision of a high density integration flash EEPROM semiconductor device having a tungsten-based gate electrode contact structure resistant to oxidation.
Additional advantages and other features of the present invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, which method comprises:
providing a semiconductor substrate comprising silicon and having a surface;
sequentially forming over the substrate a layer stack comprising:
a gate oxide layer (a) on the substrate surface,
an electrically conductive polysilicon layer (b) on the gate oxide layer,
a barrier material layer (c) on the polysilicon layer,
a tungsten layer (d) on the barrier material layer, and
a silicon nitride layer (e) on the tungsten layer;
selectively removing portions of layers (c)-(e) to define a pattern therein exposing sidewall surfaces of layers (c)-(e);
selectively forming a silicon nitride layer (f) covering the exposed sidewall surfaces of layers (c)-(c), whereby the tungsten layer (d) is encapsulated by the combination of silicon nitride layers (e) and (f) formed on the uppermost and sidewall surfaces thereof, respectively;
selectively removing portions of polysilicon layer (b) to define a pattern therein exposing sidewall surfac
Chang Chi
Huang Richard J.
Sun Yu
Yoshie Keizaburo
Advanced Micro Devices , Inc.
Chaudhari Chandra
LandOfFree
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