Method of making trench EPROM simultaneously with forming a DRAM

Details Method of making trench EPROM simultaneously with forming a DRAM Method of making trench EPROM simultaneously with forming a DRAM

1996-02-08

1999-07-27

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438259, 438270, H01L 218247

Patent

active

059306190

ABSTRACT:
A two-device nonvolatile memory cell is described. The cell comprises a planar FET and a vertical FET in series. The vertical FET has a floating gate that is predominantly capacitively coupled to a buried n well that serves as the control electrode. The structure is very similar to a trench DRAM cell, and the nonvolatile memory cell can be integrated onto a DRAM chip.

REFERENCES:
patent: 3843954 (1974-10-01), Hansen et al.
patent: 4845538 (1989-07-01), Hazani
patent: 5141886 (1992-08-01), Mori
patent: 5290725 (1994-03-01), Tanaka et al.
patent: 5389567 (1995-02-01), Acovic et al.
patent: 5399516 (1995-03-01), Bergendahl et al.

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