Method of making strained semiconductor transistors having...

Details Method of making strained semiconductor transistors having... Method of making strained semiconductor transistors having...

2008-07-08

2008-07-08

Nguyen, Thanh (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S153000, C438S154000, C257SE21001

Reexamination Certificate

active

07396714

ABSTRACT:
A process is provided for making a PFET and an NFET. Areas in a first semiconductor region adjacent to a gate stack are recessed. A lattice-mismatched semiconductor layer is grown in the recesses to apply a strain to the channel region of the PFET adjacent thereto. A layer of the first semiconductor material can be grown over the lattice-mismatched semiconductor layer and a salicide formed from the layer of silicon to provide low-resistance source and drain regions.

REFERENCES:
patent: 6228722 (2001-05-01), Lu
patent: 6417547 (2002-07-01), Kang
patent: 2004/0262683 (2004-12-01), Bohr et al.

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