Method of making silicide stop layer in a damascene...

Details Method of making silicide stop layer in a damascene... Method of making silicide stop layer in a damascene...

2001-02-12

2002-10-01

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S299000

Reexamination Certificate

active

06458679

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the formation of silicide in a damascene semiconductor structure. More particularly, the apparatus and method of the present invention allows for controlled silicidation of semiconductor material in a damascene semiconductor structure with the utilization of a silicide stop layer.
DESCRIPTION OF THE RELATED ART
Semiconductor damascene structures are well known in the semiconductor device industry. Typically, to form a damascene structure, a dielectric layer is deposited on a silicon substrate and regions are etched in the dielectric layer in a controlled manner. The etched regions may be trenches, vias, or other etched formations well-known in the art. Subsequent to the step of etching the dielectric layer, specifically chosen materials are deposited in a calculated and controlled manner in the etched regions. The deposition and formation of material layers in the trench is part of damascene semiconductor processing. Through adequate design and processing of a semiconductor structure, the semiconductor structure can operate as a semiconductor device. Examples of semiconductor devices include transistors, memory units, LEDs, and other well-known semiconductor devices.
Often one of the material layers formed in a damascene semiconductor structure is a silicide layer. The material of the silicide layer typically comprises the product of a metal or alloy reacted with a silicon material. It is often advantageous for a silicide to be formed in a semiconductor structure in a self-aligned manner. A self-aligned silicide has the advantage of being formed in a semiconductor structure without the need to selectively etch any of the silicide layer away to define the silicide regions. Silicides are often formed in damascene semiconductor structures to provide low resistivity regions for various reasons. Such reasons include the provision of interconnect structures between semiconductor devices, lowering the resistivity of a region of a semiconductor structure to enhance the operability of a semiconductor device, or other reasons that are well-known in the art.
FIGS. 1-8
exemplify the formation of silicide regions in a semiconductor damascene structure.
FIG. 1
shows silicon substrate
10
with a gate
15
and spacers
11
formed thereon. The silicon substrate
10
may be N
+
doped to form source/drain regions
13
.
FIG. 2
shows a dielectric layer
12
deposited on the silicon substrate
10
and surrounding the spacers
11
.
FIG. 3
shows the gate
15
etched to form an opening
14
down to the silicon substrate
10
.
FIG. 4
shows a dielectric layer
16
deposited in the opening
14
on the silicon substrate
10
.
FIG. 5
shows a silicon layer
18
deposited on dielectric layer
16
in the opening
14
.
FIG. 6
shows a metal layer
20
deposited on the dielectric layer
12
and on the silicon layer
18
.
FIG. 7
shows silicide layer
22
formed from the semiconductor structure shown in
FIG. 6
by a heat treatment that reacts the silicon layer
18
with the metal layer
20
to form silicide layer
22
over dielectric layer
16
. A layer of unreacted metal
21
from the metal layer
20
of
FIG. 6
remains over the dielectric layer
12
and silicide layer
22
. The unreacted metal layer
21
is typically stripped away from the semiconductor structure using conventional stripping techniques.
FIG. 8
shows the semiconductor structure of
FIG. 7
after the unreacted metal layer
21
has been stripped away. Depending on the type of silicide formed, additional heat treatment may be preformed to produce the lowest resistivity phase of the silicide.
The exemplary semiconductor structure of
FIG. 8
is a characteristic structure of a metal-oxide semiconductor field-effect-transistor (MOSFET). The silicon substrate
10
may comprise a source and a drain. Further, dielectric layer
16
may serve as a gate dielectric and silicide region
20
may serve as a gate. Typically, during the silicidation of silicon layer
18
, the entire silicon layer
18
is silicidized to form silicide layer
22
. As a result, the silicide layer
22
is in contact with dielectric layer
16
.
There are certain disadvantages to the prior art apparatus and method described above. Typically in semiconductor processing, silicon layer
18
is silicidized to form a silicide layer
22
and the entire silicon layer
18
is silicidized during a reaction with metal layer
20
during the heat treatment. This typically results in the direct contact of the silicide layer
22
with the dielectric layer
16
. This has an undesirable effect on the work function. In an ideal MOSFET it is desirable for the gate, such as formed by silicide layer
22
, and the semiconductor substrate with a source and drain, such as semiconductor substrate
10
, to have the same work function.
The work function is the minimal energy needed to remove an electron from the fermi energy level (E
F
) of a material to the vacuum energy level (E
0
). The fermi energy level is the average energy of electrons in the material in the resting state.
FIG. 9
exemplifies a band diagram of an ideal MOSFET, wherein region
23
represents a gate, region
25
represents a gate dielectric, and region
27
represents a semiconductor substrate.
FIG. 9
is characterized as being an ideal MOSFET because the work function (&phgr;
A
)
29
of region
23
and the work function (&phgr;
B
)
31
of region
27
are substantially equivalent. This characteristic prevents the effect of a bias voltage between the gate and the semiconductor substrate. For a MOSFET to operate most efficiently and effectively, the work function of the gate and the work function of the semiconductor substrate should be approximately the same, preventing an effective bias voltage.
FIG. 10
exemplifies the band diagram of a non-ideal MOSFET, wherein region
35
represents a gate and region
33
represents a semiconductor substrate that are separated by the gate dielectric represented by region
37
. The work function (&phgr;
C
)
39
of region
35
and the work function (&phgr;
D
)
41
of region
33
are not equal. An exemplary MOSFET with a band diagram of
FIG. 10
has an effective bias voltage applied to the gate. Such a bias voltage can interfere with the operation of transistor having the general structure of FIG.
8
. Transistors are, therefore, normally engineered such that the work function of the gate region and the work function of the semiconductor region are the same.
One disadvantage of the MOSFETs exemplified in
FIG. 8
is that it is difficult to control the amount of silicidation of silicon layer
18
of FIG.
6
and thereby control the work function of the gate region
22
to match the work function of the semiconductor substrate
10
. These differences in work functions result in an effective bias voltage applied to the gate of the MOSFET, which is undesirable.
SUMMARY OF THE INVENTION
There is a need for a semiconductor damascene structure in which a semiconductor layer can be silicidized in a controlled manner, to allow for the work function of the gate and the work function of the silicon substrate to be substantially equal.
These and other needs are met by embodiments of the present invention which provide a damascene semiconductor structure with a silicide stop layer which enables improved control of the silicidation of semiconductor material in a damascene semiconductor structure. A gate and spacers are formed over a semiconductor substrate. A dielectric layer is formed over the semiconductor substrate and around the spacers. The gate is etched to form an opening down to the semiconductor substrate. A first silicon layer is deposited in the opening over the semiconductor substrate. A silicide stop layer is then deposited in the opening over the first silicon layer. A second silicon layer is then deposited in the opening over the silicide stop layer. A metal layer or alloy layer is then deposited over the insulating layer and the second silicon layer and undergoes a temperature treatment. The temperature treatment caus

Affiliated with

Also associated with

Rating

Method of making silicide stop layer in a damascene... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of making silicide stop layer in a damascene..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making silicide stop layer in a damascene... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2981100