Method of making shallow junction semiconductor devices

Details Method of making shallow junction semiconductor devices Method of making shallow junction semiconductor devices

1999-05-03

2001-10-30

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S304000, C438S306000

Reexamination Certificate

active

06309937

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to the provision of an improved semiconductor device and techniques for making such a device. More particularly, but not exclusively, the present invention relates to the formation of shallow semiconductor junctions for such devices.
To increase the speed of electronic devices, it is often desirable to decrease the critical dimension of various semiconductor components. Concomitantly, functionality of many integrated circuit devices may be increased by reducing the size of individual components so that the component density, and correspondingly the number and complexity of integrated circuits formed from the components may be increased. Also, as the critical dimension of semiconductor devices is scaled down into the submicron range, it is often desirable to maintain a shallow, tightly distributed junction profile. Unfortunately, conventional processing often exposes junction forming dopants to multiple, high temperature thermal cycles that tend to deepen the corresponding profile. Consequently, there is a demand for better techniques to maintain a desired junction profile depth. Moreover, for semiconductor devices having a critical dimension deep in the submicron range (≦0.2 microns) the formation of correspondingly shallower junctions is often desired and the maintenance of such profiles often becomes even more significant for proper device performance. Thus, there is also a need for techniques to reliably provide shallower semiconductor junctions.
SUMMARY OF THE INVENTION
One form of the present invention is an improved integrated circuit device, including a shallow semiconductor junction. Alternatively or additionally, an improved integrated circuit device of another form of the present invention may include a pair of opposing sidewall spacers that each extend over a source/drain extension and overlap an adjacent source/drain region.
In another form of the present invention, a technique is provided to reduce or eliminate thermal cycles that may cause unwanted deepening of a semiconductor junction or that may otherwise undesirably redistribute junction dopants. This technique maybe used to provide a device with an ultra-shallow junction. As used herein, “an ultra-shallow junction” refers to a junction having a maximum depth of less than about 1000 Angstroms (Å) with a dopant level of at least 10
19
cm
−3
. Moreover, ultra-shallow junctions having a preferred depth of less than about 500 Å may be provided in accordance with this form.
In yet another form, an integrated circuit device is doped with one or more masking members located to selectively block doping of certain substrate regions. These members are then removed and at least a portion of each of the blocked regions is doped with a different profile characteristic relative to the first doping process. After the second doping process, new blocking or masking members may be formed that cover at least a portion of the regions doped to the second nonzero level. These new masking members may be sized differently than the masking members that were removed. In one variation of this form, the new masking members are configured as transistor gate spacers that may be sized and shaped to facilitate subsequent processing, such as suicide formation.
In a different form of the present invention, a method comprises doping an integrated circuit substrate to provide a first pair of doped substrate regions, with a transistor gate member and a corresponding first pair of spacers extending from the substrate between the first doped regions. The first spacers are then removed. After spacer removal, doping of the substrate takes place to provide a second pair of doped substrate regions with a different profile than the first doped regions. These second doped regions are each positioned along the substrate between a corresponding one of the first doped regions and the gate member. The substrate is heated to activate dopant of the first and second doped regions. A second pair of spacers is formed about the gate member after the second doped regions are formed. A suicide contact is provided on at least one of the first doped regions or the gate member after formation of the second pair of spacers.
Another form of the present invention includes performing a first dopant implant into a source region and a drain region of an integrated circuit substrate. A transistor gate member extends from the substrate between the source and drain regions, and a first pair of spacers bounds the gate member with one of the first spacers masking a first region between the source region and the gate member during the first implant and another of the first spacers masking a second region between the drain region and the gate member during first implant. The first spacers are each formed from tetraethylorthosilicate (TEOS). The first spacers are etched away after the first implant, and a second dopant implant is performed to dope the first and second regions relative to the source and drain regions with a dopant of the same conductivity type as implanted in the source and drain regions. A second pair of spacers are then formed about the gate member.
Yet another form includes providing an integrated circuit substrate with a transistor gate member extending therefrom that is bounded by a first pair of spacers, and doping the substrate to provide a first pair of doped substrate regions. The gate member and the first spacers are positioned between the first doped regions. The first spacers are removed and the substrate is doped after the first spacer removal to provide a second pair of doped substrate regions. The second doped substrate regions are each positioned along the substrate between a corresponding one of the first doped regions and the gate member. A second pair of spacers are formed that each extend along the substrate from a sidewall of the gate member over a corresponding one of the second doped regions, and that each include a downwardly sloped surface positioned below a top surface of the gate member. The second spacers may each be wider than a respective one of the first spacers to at least partially extend over a corresponding one of the first doped regions.
Accordingly, it is one object of the present invention to provide an improved electronic device.
It is another object of the invention to provide techniques for manufacturing a shallow junction semiconductor device.
Further objects, features, aspects, forms, embodiments, benefits, and advantages of the present invention shall become apparent from the description and drawings contained herein.


REFERENCES:
patent: 4728617 (1988-03-01), Woo et al.
patent: 4784965 (1988-11-01), Woo et al.
patent: 4978626 (1990-12-01), Poon et al.
patent: 4994404 (1991-02-01), Sheng et al.
patent: 5168072 (1992-12-01), Moslehi
patent: 5200352 (1993-04-01), Pfiester
patent: 5514610 (1996-05-01), Wann et al.
patent: 5527721 (1996-06-01), Farb
patent: 5585295 (1996-12-01), Wu
patent: 5595919 (1997-01-01), Pan
patent: 5610088 (1997-03-01), Chang et al
patent: 5693546 (1997-12-01), Nam et al.
patent: 5736446 (1998-04-01), Wu
patent: 5747372 (1998-05-01), Lim
patent: 5750430 (1998-05-01), Son
patent: 5759897 (1998-06-01), Kadosh et al.
patent: 5770506 (1998-06-01), Koh
patent: 5780350 (1998-07-01), Kapoor
patent: 5783475 (1998-07-01), Ramaswami
patent: 5895955 (1999-04-01), Gardner et al.
patent: 5946581 (1999-08-01), Gardner et al.
patent: 6040222 (2000-03-01), Hsu et al.
patent: 0 450 432 A1 (1991-10-01), None
patent: 04 023439 A (1992-01-01), None
English Abstract of Japanese Patent Publication, 04 023439A, Date of Publication Jan. 27, 1992.

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