Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-05-15
2004-02-10
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S261000, C438S978000
Reexamination Certificate
active
06689659
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of manufacturing the same. More particularly, the present invention relates to a floating gate of a semiconductor memory device and a method of forming the same.
2. Description of the Related Art
Semiconductor memory devices are generally of two types, a random access memory (RAM), such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), which may be referred to as a volatile memory device in which the stored data on the cell is destroyed if power is interrupted and a read only memory (ROM), which may be referred to as a non-volatile memory device in which the stored data on the cell is retained even when the power is temporarily interrupted.
Since the non-volatile memory device has a capability of storing data for an unlimited time, there is an increased demand for a flash memory device such as electrically erasable and programmable ROM (EEPROM) capable of inputting and outputting data electrically. Memory cells of these memory devices may have a vertically laminated gate structure including a floating gate formed on a silicon substrate. Memory cells having a multi-layered gate structure typically include at least one tunnel oxide layer or dielectric layer and a control gate formed on or adjacent to the floating gate. In a flash memory cell having the above structure, storing the data is accomplished as an acceptable voltage is applied to the control gate and the substrate to introduce or extract electrons in/from the floating gate. A dielectric layer maintains the electric potential on the floating gate.
FIGS. 1A and 1B
are sectional views of the flash memory cell according to the conventional art, in which
FIG. 1A
is a sectional view of the flash memory cell, taken along a bit line and
FIG. 1B
is a sectional view of the flash memory cell, taken along a word line.
Referring to
FIGS. 1A and 1B
, a tunnel oxide layer
12
is formed on a semiconductor substrate
10
in which a field region
11
is formed. A floating gate
14
is formed on tunnel oxide layer
12
. A dielectric layer
16
is formed on the floating gate
14
and a control gate
20
is formed on the floating gate
14
.
The floating gate
14
is formed on an active region and extended to portions of the field region
11
on both sides of the active region
11
. The control gate
20
is provided as a word line and has a polycide structure in which a doped poly-silicon layer
18
and a metal silicide layer
19
are laminated in order to lower a resistance value thereof.
Since a high coupling ratio should be maintained between the floating gate
14
and the control gate
20
in order to induce a voltage applied to the control gate
20
to the floating gate
14
, a thickness of the dielectric layer
16
should be small to increase a capacity thereof. Furthermore, the dielectric layer
16
should have an electric charge retention characteristic such that electric charge is not leaked from the charged floating gate
14
.
It is fairly difficult to form a thin thermal oxide film on the floating gate
14
including doped poly-silicon because of the increase in leakage current. As a result, a composite layer including a first oxide layer, a nitride layer and a second oxide layer of which dielectric constant is higher than a single oxide layer is currently used as the dielectric layer
16
. After growing the first oxide layer by a thermal oxidation process, the nitride layer is deposited on the first oxide layer by a low-pressure chemical vapor deposition (LPCVD) method. Then, the second oxide layer is grown on the nitride layer by the thermal oxidation process.
Because an edge of the floating gate
14
is sharp, a thickness of the dielectric layer
16
is smaller at the edge of the floating gate
14
when the dielectric layer
16
is formed (illustrated at circle “A” in FIG.
1
B). Therefore, an electric field is concentrated at the edge of the floating gate
14
which increases the leakage current. This causes endurance and data retention characteristics of the memory cell to be deteriorated.
These problems may occur even though the dielectric layer
16
is formed by a chemical vapor deposition (CVD) method in order to reduce the thickness of the dielectric layer
16
thinner, instead of a thermal oxidation process.
SUMMARY OF THE INVENTION
The present invention provides a non-volatile memory device in which an edge of a floating gate is rounded.
The present invention also provides a method of manufacturing a non-volatile memory device in which an edge of a floating gate is rounded to reduce the deterioration of endurance and data retention characteristics.
The present invention provides a semiconductor memory device including a substrate having a defined active region, an insulation layer formed on the active region of the substrate, and a floating gate formed on the insulation layer, with at least one rounded edge.
The present invention also provides a method of manufacturing a semiconductor memory device including forming a field oxide layer on a semiconductor substrate to divide the semiconductor substrate into a active region and a field region; forming a tunnel oxide layer on the semiconductor substrate, depositing a conductive layer for forming a floating gate on the tunnel oxide layer, partially etching the conductive layer on the field region to form a conductive layer pattern, and rounding at lest one edge of the conductive layer pattern.
In the present invention, an annealing of the semiconductor substrate may carried out in an ambient atmosphere of hydrogen gas after the conductive layer for the floating gate is patterned. Alternatively, an entire surface of the conductive layer may be etched by dry or wet etching, to thereby round at least one edge of the conductive layer pattern. As a result, the dielectric layer, which is formed on the floating gate, is not thinner at an edge of the floating gate.
REFERENCES:
patent: 5830771 (1998-11-01), Fukatsu et al.
patent: 5836772 (1998-11-01), Chang et al.
patent: 6284598 (2001-09-01), Kelley et al.
patent: 6387756 (2002-05-01), Muramatsu
patent: 07-058221 (1995-03-01), None
patent: 08-083854 (1998-11-01), None
Huh Hyoung-Jo
Kang Man-Sug
Chaudhari Chandra
Harness & Dickey & Pierce P.L.C.
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