Method of making semiconductor device with decreased channel wid

Details Method of making semiconductor device with decreased channel wid Method of making semiconductor device with decreased channel wid

1999-01-05

2000-08-15

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438302, 438919, H01L 218238

Patent

active

061035629

ABSTRACT:
Semiconductor device and method for fabricating the same, is disclosed, which can maintain a threshold voltage constant despite of decreased channel width, the device including a first, and a second conductive type wells in a substrate, a first, and a second gate insulating films on the first, and the second conductive type wells, a first gate electrode on the first gate insulating film, the first gate electrode being doped with a second conductive type except for edges of the first gate electrode in a channel width direction counter doped with a first conductive type, a second gate electrode on the second gate insulating film, the second gate electrode being doped with a first conductive type except for edges of the second gate electrode in a channel width direction counter doped with a second conductive type, and isolating regions formed between the first, and second conductive type wells, the first, and second gate insulating films, and the first, and second gate electrodes.

REFERENCES:
patent: 4943537 (1990-07-01), Harrington, III
patent: 5413945 (1995-05-01), Chien et al.
patent: 5834347 (1998-11-01), Fukatsu et al.
Schwalke, U. et al., "Extigate: The Ultimate Process Architecture for sub-0.25.mu.m CMOS Technologies", Proceedings of the 26th European Solid State Device Research Conference, 1996, pp. 317-320.

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