Method of making semiconductor device having double spacer

Details Method of making semiconductor device having double spacer Method of making semiconductor device having double spacer

1998-09-23

2001-03-27

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S299000, C438S305000, C438S595000

Reexamination Certificate

active

06207519

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device having a double spacer and a method of making the same to enhance the reliability of the semiconductor device.
2. Discussion of Related Art
The miniaturization of devices according to a scaling rule is used in a semiconductor device to achieve large-scale integration and high-speed operation. In MOS devices, this leads to a decrease in the threshold voltage due to shortening of the channel. Also, the effect of a depleted layer upon the channel in a source/drain region is reduced so as to attain a stable threshold voltage in the semiconductor device. To meet the requirements such as large-scale integration and high operational speed, semiconductor devices generally have a pocket implantation region or thin junction layer formed by a rapid heat treatment to increase the concentration of dopants in a localized region of the substrate.
FIGS. 1-3
contain schematic cross-sectional diagrams illustrating a method of fabricating a prior art semiconductor device. In the prior art device illustrated in
FIGS. 1-3
, a device separating region
12
is formed in a p-type silicon substrate
10
by a known LOCOS step. As shown in
FIG. 1
, a gate oxide layer
14
is formed on the upper surface of the active region of a silicon substrate
10
, and a conductive layer is formed on the gate oxide layer
14
. The conductive layer is subjected to photolithographic and etching steps to form a gate electrode
16
. A buffer oxide layer
18
is deposited on the the gate electrode
16
by an oxidation step. Using the buffer oxide layer
18
as a mask, arsenic (As) is typically lightly implanted as an n-type impurity to form a lightly doped LDD region
20
which self aligns at the edge of the gate electrode
16
in the vicinity of the surface of the silicon substrate
10
.
Referring to
FIG. 2
, an oxide layer is then formed on the structure as an insulating layer. The structure is then subjected to a back-etching step to form a spacer
22
on the sidewalls of the gate electrode
16
.
As shown in
FIG. 3
, using the spacer
22
as a mask, boron (B) is implanted as a p-type impurity in a medium concentration and at the same time arsenic (As) is heavily implanted as an n-type impurity. This results in a B-doped pocket implantation region
24
and an As-doped source/drain region
26
which self-align at the edge of the spacer
22
in the vicinity of the surface of the silicon substrate
10
. The resulting product is then subjected to a rapid heat treatment step so that the pocket implantation region
24
has a shape surrounding the source/drain region
26
.
One drawback to this prior art approach is that the semiconductor device is generally subjected to a very rapid heat treatment at high temperature for a short time in order to form a thin junction. This makes it very difficult to diffuse dopants of the pocket implantation region
24
in a controlled fashion to a desired depth, i.e., under the source/drain region
26
. This can result in device reliability problems and reduced device performance.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a semiconductor device having a double spacer and its fabricating method which substantially obviate one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a double spacer on the sidewalls of a gate electrode such that a pocket implantation region can be formed stably to a desired depth under a source/drain region with increased concentration compared to the substrate, thus enhancing the reliability of the semiconductor device, especially in devices having channel lengths between 0.3 and 0.5 &mgr;m.
To achieve these and other objects and advantages, the semiconductor device in accordance with the invention includes a gate insulating layer formed over the surface of a semiconductor substrate and a gate electrode formed over the gate insulating layer. A first spacer is formed over the sidewall of the gate electrode, and a second spacer is formed over the sidewall of the first spacer. A first impurity region doped with a first conductivity type impurity at a first concentration is formed at a first junction depth in the substrate to self-align near the edge of the gate electrode. A second impurity region doped with a second conductivity type impurity at a second concentration is formed at a second junction depth in the substrate to self-align near the edge of the first spacer. A third impurity region doped with the first conductivity type impurity at a third concentration is formed at a third junction depth in the second impurity region to self-align near the edge of the second spacer. The third junction depth is less than the second junction depth.


REFERENCES:
patent: 5089865 (1992-02-01), Mitsui et al.
patent: 5091763 (1992-02-01), Sanchez
patent: 5278441 (1994-01-01), Kang et al.
patent: 5716866 (1998-02-01), Dow et al.

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