Method of making semiconductor device having an insulating...

Details Method of making semiconductor device having an insulating... Method of making semiconductor device having an insulating...

2000-11-01

2002-08-27

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S382000, C438S637000

Reexamination Certificate

active

06440790

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a semiconductor device and a method of fabricating the same. More specifically, the invention relates to a semiconductor device including a plurality of transistors, and a plurality of load or capacitance elements, and a method of fabricating the same.
BACKGROUND ART
A static random-access memory (hereinafter abbreviated to “SRAM”) will be described as an example of conventional semiconductor devices. A conventional flip-flop SRAM cell comprises two load elements and four n-channel MOS transistors, as described in JP-B No. 7-112014, and T. Yamanaka, T. Hashimoto et al. “A 25 &mgr;m
2
, New poly-Si PMOS Load (PPL) SRAM Cell Having Excellent Soft Error Immunity”, IEDM '88.
FIG. 75
illustrates an equivalent circuit of a conventional flip-flop SRAM cell, wherein the drain D of each of a pair of drive MOS transistors T
1
and T
2
is connected to the gate electrode G of the other. Load elements, for example, load resistors R
1
and R
2
of high-resistance polysilicon, are connected to the drains D of the drive MOS transistors T
1
and T
2
. The sources S of the drive MOS transistors T
1
and T
2
are maintained at a predetermined potential, for example a ground potential, and a supply voltage VCC is applied to the other ends of the load resistors R
1
and R
2
. Supply voltage Vcc supplies a small current to a flip-flop circuit including the drive MOS transistors T
1
and T
2
, and the load resistors R
1
and R
2
. Access MOS transistors T
3
and T
4
are connected to storage nodes N
1
and N
2
. The four MOS transistors T
1
to T
4
, and the two load resistors R
1
and R
2
constitute a cell of one bit. In
FIG. 75
, reference numeral
10
a
represents a word line and reference numerals
50
a
and
50
b
represent bit lines.
FIG. 76
is an equivalent circuit of a flip-flop SRAM cell provided with thin-film transistors (“TFTs”) as load elements. Generally, load elements are high-resistance polysilicon resistors or thin-film transistors.
The prior art will be described in detail with reference to
FIGS. 77
to
86
.
FIGS. 77
to
81
illustrate the structure of a conventional SRAM cell of a highresistance load type for one bit and a method of fabricating the same.
FIGS. 77
to
80
show a planar layout of each layer forming a SRAM cell for one bit.
FIG. 81
is a sectional view taken on line Y
1
-Y
2
of
FIGS. 77
to
80
.
FIG. 77
is a planar layout of access MOS transistors and drive MOS transistors, including a first conductive film serving as a gate electrode.
FIG. 78
is a pattern of a second conductive film of high-resistance polysilicon formed in part of a polysilicon film.
FIG. 79
is a pattern of a third conductive film.
FIG. 80
is a pattern of a fourth conductive film forming aluminum lines.
Referring to
FIG. 77
, a word line
10
a
formed by patterning a first conductive film serves as a common gate shared by access MOS transistors T
3
and T
4
. The drains
6
a
and
6
b
, i.e., diffused layers, of the access MOS transistors T
3
and T
4
are connected through viaholes
21
a
and
21
b
to members
30
a
and
30
b
of a third conductive film, as shown in
FIGS. 79 and 81
. The drains
6
a
and
6
b
are also connected through viaholes
42
a
and
42
b
to bit lines
50
a
and
50
b
, i.e., portions of a fourth conductive film of aluminum or the like as shown in
FIGS. 80 and 81
.
The gate electrodes
10
b
and
10
c
of drive MOS transistors T
2
and T
1
are connected through viaholes
5
a
and
5
c
to the sources
6
c
and
6
d
of the access MOS transistors T
3
and T
4
, respectively. The sources of the drive MOS transistors T
1
and T
2
are connected through viaholes
21
c
and
21
d
by a third conductive film
30
c
as shown in
FIG. 79. A
ground potential VSS is applied through the third conductive film
30
c
to the sources of all the drive MOS transistors of the SRAM.
The sources
6
c
and
6
d, i.e., diffused layers, of the access MOS transistors T
3
and T
4
are connected through viaholes
12
a
and
12
b
to low-resistance polysilicon films
20
a
and
20
b
, and to resistors, i.e., high-resistance films,
20
R
1
and
20
R
2
, respectively, as shown in FIG.
78
. As shown in
FIG. 78
, a second conductive film
20
c
forms a power feed line for applying a supply voltage VCC to high-resistance elements R
1
and R
2
.
FIGS. 82
to
86
illustrate the structure of the one cell for one bit of the conventional SRAM of a TFT load type shown in FIG.
76
.
FIGS. 82
to
85
show the planar layout of each cell in different phases of the fabricating process.
FIG. 86
is a sectional view taken on line Y
1
-Y
2
in
FIGS. 82
to
85
.
FIG. 82
is a planar layout of access MOS transistors and drive MOS transistors including a first conductive film forming gate electrodes.
FIG. 83
is a plan view of a second conductive film serving as a lower gate electrode of a TFT.
FIG. 84
is a plan view of a third conductive film serving as a channel of the TFT.
FIG. 85
is a plan view of aluminum wiring lines formed by patterning a fifth conductive film.
Referring to
FIG. 82
, a word line
10
a
is a common gate shared by access MOS transistors T
3
and T
4
. The drain
6
b
, i.e., a diffused layer, of the access MOS transistor T
4
is connected through a viahole
32
b
to a fourth conductive film
40
b
. The drain
6
b
is also connected through a viahole
41
b
to bit lines
50
a
and
50
b
, i.e., aluminum wiring lines formed by patterning a fifth conductive film as shown in
FIGS. 85 and 86
. Similarly, the drain
6
a
, i.e., a diffused layer, of the access MOS transistor T
3
is connected through a viahole
32
a
to a fourth conductive film
40
a
. The drain
6
a
is also connected through a viahole
41
a
to the bit lines
50
a
and
50
b
, i.e., aluminum wiring lines formed by patterning the fifth conductive film.
The sources
6
c
and
6
d
of the access MOS transistors T
3
and T
4
are connected through viaholes
5
a
and
5
c
to the gate electrodes
10
b
and
10
c
of drive MOS transistors T
2
and T
1
, respectively, as shown in FIG.
82
. The sources of the drive MOS transistors T
1
and T
2
are interconnected by a diffused region, as shown in
FIG. 82. A
first conductive film
10
d
is connected to the sources of all the drive MOS transistors of the SRAM to apply a ground potential VSS to the sources.
TFTs T
5
and T
6
, i.e., load elements, comprise lower gate electrodes
20
a
and
20
b
formed by patterning a second conductive film of polysilicon (as shown in FIGS.
83
and
86
), a second insulating film
21
serving as a gate oxide film (as shown in FIG.
86
), and polysilicon channels
30
a
and
30
b
formed by patterning a third conductive film (as shown in FIGS.
84
and
86
).
As shown in
FIGS. 82
to
86
, nodes N
1
and N
2
, i.e., the diffused sources of the access MOS transistors T
3
and T
4
, are connected through viaholes
12
a
and
21
a
and viaholes
12
b
and
21
b
to channel layers
30
a
and
30
b
formed by patterning a third conductive film, respectively. The opposite ends of the channel layers
30
a
and
30
b
are low-resistance polysilicon. The other end of the low-resistance polysilicon layer serves as a power feed line for feeding power of a supply voltage VCC.
The foregoing conventional SRAM cell has the following problems.
When forming the high-resistance polysilicon layer to be used as load elements and the TFTs in a layered structure on a memory cell, the high-resistance polysilicon layer and the TFTs are connected through the viaholes
5
a
and
5
b
to the gate electrodes
10
b
and
10
c
of the drive MOS transistors T
1
and T
2
. Misalignment of masks (masks for forming the gate electrodes
10
b
and
10
c
of the drive MOS transistors T
1
and T
2
and the viaholes
12
a
and
12
b
, and masks for forming the viaholes
12
a
and
12
b
and the load elements) for forming the viaholes
5
a
and
5
b
and the gate electrodes
10
b
and
10
c
of the drive MOS transistors T
1
and T
2
, results in an increase in the dimensions of those components (hereinaf

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