Method of making self-aligned silicide narrow gate electrodes fo

Details Method of making self-aligned silicide narrow gate electrodes fo Method of making self-aligned silicide narrow gate electrodes fo

1997-01-22

1998-03-24

Niebling, John

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438532, 438533, 438586, H01L 21336

Patent

active

057312397

ABSTRACT:
A method for making low sheet resistance sub-quarter-micrometer gate electrode lengths on field effect transistors has been achieved. The method involves patterning gate electrodes on a silicon substrate from a conductively doped polysilicon layer having a silicon nitride layer on the surface. After forming the FET lightly doped drains (LDD), the sidewall spacers, and the heavily doped source/drain contact regions with titanium contacts, an insulating layer is chemically/mechanically polished back to the silicon nitride or silicon oxynitride on the gate electrode layer to form a planar self-aligning mask. A pre-amorphizing implantation is carried out, and a titanium silicide is selectively formed on the gate electrodes resulting in small grain sizes and much reduced sheet resistance. The self-aligned mask prevents ion implant damage to the shallow source/drain regions adjacent to the FET gate electrodes. A second embodiment uses the self-aligned mask to form selectively a cobalt silicide on the polysilicon gate electrodes for low sheet resistance, while preventing the cobalt silicide from reacting with the adjacent titanium silicide source/drain regions.

REFERENCES:
patent: 5334545 (1994-08-01), Caviglia
patent: 5447874 (1995-09-01), Grivna et al.
patent: 5494857 (1996-02-01), Cooperman et al.
J.A. Kittl et al. "A Ti Salicide Process for 0.01 .mu.m Gate Length CMOS Technology", Published in 1986 Symposium of VLSI Technology Digest of Technical Papers, pp. 14-15.

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