Method of making planar double gate silicon-on-insulator...

Details Method of making planar double gate silicon-on-insulator... Method of making planar double gate silicon-on-insulator...

2008-03-11

2008-03-11

Trinh, Michael (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S151000, C438S157000, C438S284000, C257SE21421

Reexamination Certificate

active

11142057

ABSTRACT:
Methods are provided for forming a semiconductor device from a substrate comprising a bottom gate layer, a channel layer overlying the bottom gate layer, and a top gate structure formed over the channel layer. First, a hardmask comprising a first material interposed between a second material and a third material is deposited over a portion of the top gate structure. Then, the hardmask and top gate structure are encapsulated with an insulating material to form a spacer. A channel structure is formed from the channel layer, and the channel structure is disposed under the spacer. A bottom gate structure is formed from the bottom gate layer, and the bottom gate structure is disposed under the channel structure. Then, a source/drain contact is formed around the bottom gate structure.

REFERENCES:
patent: 6004853 (1999-12-01), Yang et al.
patent: 6339002 (2002-01-01), Chan et al.
patent: 6642115 (2003-11-01), Cohen et al.
patent: 7141476 (2006-11-01), Dao
patent: 2004/0031979 (2004-02-01), Lochtefeld et al.
patent: 2004/0197977 (2004-10-01), Deleonibus
Van Meer and De Meyer (IMEC), “The Spacer/Replacer Concept: A Viable Route for Sub-100nm Ultrathin-Film Fully-Depleted SOI CMOS,” IEEE-EDL vol. 23, No. 1, Jan. 2002, pp. 46-48.
Disclosure for Freescale U.S. Appl. No. 10/871,402 filed on Jun. 18, 2004.
Disclosure for Freescale U.S. Appl. No. 10/971,657 filed on Oct. 22, 2004.

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