Method of making NVRAM cell with planar control gate

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

438258, H01L 218247

Patent

active

058997130

ABSTRACT:
A nonvolatile memory cell utilizing planar control gates, which provides advantages of being compatible with self-aligned silicide processes and providing a planar surface for subsequent wiring processes. A substrate defines a first NVRAM region having large floating gate areas with smaller areas cutout to isolate individual memory cells, and a second CMOS Logic region. ONO is deposited on the floating gate areas, and a thick poly layer is deposited in a blanket manner over the first and second regions of the substrate. Resist shapes are patterned over the logic areas in the array where necessary according to a predetermined density algorithm. The poly layer is reactive ion etched, followed by a chemical mechanical polishing (CMP) operation. The final poly gate thickness is 200-220 nm in the CMOS logic areas and in the NVRAM control gate areas between floating gate regions, but only 100-120 nm for the NVRAM control gates over the floating gates. The control gate physical thickness is decoupled (isolated) from the standard logic by standard photoetching processes, and the final structure appears identical from a topological perspective to a standard CMOS structure.

REFERENCES:
patent: 4458407 (1984-07-01), Hoeg, Jr. et al.
patent: 4516313 (1985-05-01), Turi et al.
patent: 5120670 (1992-06-01), Bergmont
patent: 5208179 (1993-05-01), Okazawa
patent: 5238855 (1993-08-01), Gill
patent: 5304503 (1994-04-01), Yoon et al.
patent: 5411904 (1995-05-01), Yamanchi et al.
patent: 5420060 (1995-05-01), Gill et al.
patent: 5464999 (1995-11-01), Bergemont
patent: 5496756 (1996-03-01), Sharma et al.
patent: 5512503 (1996-04-01), Hong

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method of making NVRAM cell with planar control gate does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of making NVRAM cell with planar control gate, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making NVRAM cell with planar control gate will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1865218

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.