Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-03-18
1998-12-22
Chaudhari, Chandra
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438588, H01L 218247
Patent
active
058518800
ABSTRACT:
A simplified manufacturing process of a semiconductor memory 10, in which after a layer-built structure is formed of a control-gate conductive layer 19, an intergate insulating film 17, and a floating-gate conductive layer 18, a contact hole for a connector 21 for connecting the floating-gate conductive layer 18 and the control-gate conductive layer 19 together is formed in two stages: by forming a first contact hole 24 passing through the control-gate conductive layer 19 and opening above the intergate insulating film 17, and then forming a second contact hole 26 passing through the intergate insulating film 17 and opening to the floating-gate conductive layer 18, and the first contact hole 24 is formed in conjunction with patterning of a control gate g1, and the second contact hole 26 is formed in conjunction with the formation of a drain contact hole 20.
REFERENCES:
patent: 4780431 (1988-10-01), Maggioni et al.
patent: 4822750 (1989-04-01), Perlegos et al.
patent: 5597750 (1997-01-01), Pio et al.
patent: 5702966 (1997-12-01), Noda et al.
Chaudhari Chandra
OKI Electric Industry Co., Ltd.
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