Method of making nonvolatile memory cell with vertical gate over

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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438262, 438453, 438773, H01L 218247

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active

056610556

ABSTRACT:
A memory device, such as a flash EEPROM, has zero birds' beaks and vertically overlapping gates to facilitate high cell density in the EEPROM's core. During fabrication, a layer of field oxide is formed over the core. The active regions are exposed by etching through the layer of field oxide to form vertically walled cavities around the active regions. The tunnel oxide, floating gate, interpoly dielectric, and the control gate are formed within each cavity so that the floating gate overlaps the control gate along the vertical walls. As a result, capacitive coupling between the gates is maintained, yet the horizontal dimensions of the cell decrease. Similarly, the absence of birds' beaks facilitates higher cell density in the core.

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"Physical and Electrical Characterization of a SILO Isolation Structure," Deroux-Dauphin, et al., IEEE Transactions of Electron Devices, vol., ED-32, No. 11, p. 2392, Nov., 1985.
"Electrical Properties for MOS LSI's Fabricated Using Stacked oxide SWAMI Technology," Sawada, et al., IEEE Transactions on Electron Devices, Col. ED-32, No. 11, p. 2243, Nov. 1985.

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