Method of making non-volatile memory with sharp corner

Details Method of making non-volatile memory with sharp corner Method of making non-volatile memory with sharp corner

2001-03-08

2003-09-16

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S304000, C438S596000

Reexamination Certificate

active

06620687

ABSTRACT:

The present invention relates to a semiconductor device, and more specifically, to a method of fabricating a nonvolatile memory that includes a floating gate having sharp corners.
BACKGROUND OF THE INVENTION
The semiconductor industry has been advanced to the field of Ultra Large Scale Integrated (ULSI) technologies. The fabrication of the nonvolatile memories also follows the trend of the reduction of the size of a device. The high-density nonvolatile memories can be applied as the mass storage of portable handy terminals, solid state camera and PC cards. That is because that the nonvolatile memories exhibit many advantages, such as a fast access time, low power dissipation, and robustness. Further, it can be used to replace magnetic disk memory.
The nonvolatile memories include various types of devices, such as EAROM (electrically alterable read only memory), EEPROM (electrically erasable programmable read only memory), EEPROM-EAROMs and non-volatile SRAMs. Different types of devices have been developed for specific applications requirements in each of these segments. These parts have been developed with a focus on the high endurance and high speed requirements. In such device, electrical alterability is achieved by Fowler-Nordheim tunneling which is cold electron tunneling through the energy barrier at a silicon-thin dielectric interface and into the oxide conduction band. Typically, the thin dielectric layer is composed of silicon dioxide and the thin silicon dioxide layer allows charges to tunnel through when a voltage is applied to the gate. These charges are trapped in the silicon dioxide and remain trapped there since the materials are high quality insulators.
Various nonvolatile memories have been disclosed in the prior art. For example, Mitchellx has proposed EPROMs with self-aligned planar array cell. In this technique, buried diffusion self-aligned to the floating gate avalanche injection MOS transistor is used for the bit lines. See “A New Self-Aligned Planar Cell for Ultra High Density EPROMs, A. T. Mitchellx, IEDM, Tech. pp. 548-553, 1987”. Bergemont proposed another cell array for high density flash EEPROM, which can be seen in “NOR Virtual Ground (NVG)—A New Scaling Concept for Very High Density FLASH EEPROM and its Implemntation in a 0.5 &mgr;m Process, A Bergemont, IEEE, pp. 15-18, 1993”. This cell structure is introduced for scaling down the size of the devices to fabricate high density EEPROMs. Another prior art that relates to the field is disclosed in the U.S. Pat. No. 4,203,158.
However, most of such device includes a floating gate transistor and a separate select transistor for each storage site. These structures occupies larger area, it does not meet the trend of the technology. One prior art discloses single transistor nonvolatile device. Please refer to U.S. Pat. No. 5,029,130 to Bing Yeh, which assigned to Silicon Storage Technology. In the prior art, Bing Yeh disclosed a device with sharp corner to improve the performance of the device.
SUMMARY OF THE INVENTION
The object of the present invention is to form one single transistor nonvolatile memory that includes shape corners to improve the efficiency of electron injection.
A method for manufacturing one single transistor nonvolatile memory is disclosed. The method comprises forming a first dielectric layer on the semiconductor substrate as a gate dielectric. A first conductive layer is formed on the first dielectric layer, and a second dielectric layer is then formed thereon. The second dielectric layer and the first conductive layer are next patterned. Subsequently, conductive spacers with sharp corners are created by well know anisotropical etching. A tunneling dielectric layer is then formed on the surface of a floating gate consisting of the spacers and patterned structure. A second conductive layer is formed on the tunneling dielectric layer as a control gate.


REFERENCES:
patent: 5652161 (1997-07-01), Ahn
patent: 6171909 (2001-01-01), Ding et al.
patent: 6261903 (2001-07-01), Chang et al.
patent: 6331464 (2001-12-01), Liou et al.
patent: 6355525 (2002-03-01), Nakagawa

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