Method of making non-volatile memory with polysilicon spacers

Details Method of making non-volatile memory with polysilicon spacers Method of making non-volatile memory with polysilicon spacers

2000-01-31

2001-05-22

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S296000, C438S304000, C438S596000

Reexamination Certificate

active

06235589

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 12-001834, filed Jan. 7, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a non-volatile semiconductor memory and, more particularly, to a semiconductor device having a memory cell array structure and a method of fabricating the same.
There is a non-volatile semiconductor memory which has a gate electrode with a miniaturized double-layer stacked structure and memory transistors. The following describes a method of fabricating a non-volatile semiconductor memory having a memory cell array structure according to one prior art.
First, as shown in
FIG. 23
, a gate oxide film
12
having a thickness of, for example, 80 Å is formed on a silicon substrate
11
, and a first polycrystalline silicon film
13
having a thickness of, for example, 1000 Å is formed on this gate oxide film
12
. Formed on this first polycrystalline silicon film
13
is a silicon nitride film
14
with a thickness of, for example, 1500 Å, which becomes an etching mask material.
Next, as shown in
FIG. 24
, a resist
14
a
is formed on the silicon nitride film
14
and is then patterned by photolithography. With the patterned resist
14
a
as a mask, the silicon nitride film
14
is removed by anisotropic dry etching. Thereafter, the resist
14
a
is removed by wet etching.
Then, as shown in
FIG. 25
, with the patterned silicon nitride film
14
as a mask, the first polycrystalline silicon film
13
, the gate oxide film
12
and the silicon substrate
11
are etched to a desired depth by anisotropic dry etching, thereby forming trenches
15
.
Then, as shown in
FIG. 26
, an oxide film
16
having a thickness of, for example, 100 Å is formed on the exposed surfaces of the silicon substrate
11
and the first polycrystalline silicon film
13
in order to recover from the damage on the etched surface of the silicon substrate
11
.
Next, a buried insulating film
17
with a thickness of, for example, 6000 Å is formed on the entire surface, burying the trenches
15
, as shown in FIG.
27
. The buried insulating film
17
is then planarized to the desired height by CMP (Chemical Mechanical Polish), thus exposing the surface of the silicon nitride film
14
. Thereafter, the silicon nitride film
14
is removed by wet etching, forming device regions
11
a
and device isolation regions
11
b
, as shown in FIG.
28
.
Then, as shown in
FIG. 29
, a second polycrystalline silicon film
18
having a thickness of, for example, 1000 Å is formed on the entire surface. Then, a resist
14
b
is deposited on the second polycrystalline silicon film
18
and is patterned as shown in FIG.
30
. With this patterned resist
14
b
as a mask, the second polycrystalline silicon film
18
is removed by anisotropic dry etching, thereby forming slits
18
b
, as shown in FIG.
31
. Thereafter, the resist
14
b
is removed.
Then, an ONO film (a multilayer film consisting of a silicon oxide film/silicon nitride film/silicon oxide film)
19
having a thickness of, for example, 120 Å is formed on is formed on the entire surface, as shown in FIG.
32
. Then, as shown in
FIG. 33
, a third polycrystalline silicon film
20
with a thickness of, for example, 1000 Å is formed on the ONO film
19
, a high-melting-point silicide film
21
with a thickness of, for example, 500 Å is formed on is formed on this third polycrystalline silicon film
20
.
Thereafter, to form word lines, the high-melting-point silicide film
21
, the third polycrystalline silicon film
20
, the ONO film
19
, the second polycrystalline silicon film
18
and the first polycrystalline silicon film
13
are processed in order by anisotropic dry etching. Through the above procedures, memory cells (not shown) are formed.
According to this conventional non-volatile memory, a voltage of about 20 V is applied to the high-melting-point silicide film
21
, thereby generating FN (Fowler-Nordherm) current in the gate oxide film
12
. As a result, electrons are injected into the first polycrystalline silicon film
13
. Meanwhile, a voltage of about 20 V is applied to the silicon substrate
11
, thereby generating FN current in the gate oxide film
12
. Accordingly, electrons are emitted from the first polycrystalline silicon film
13
.
The injection and emission of electrons are accomplished by the FN current that is generated in the gate oxide film
12
. The level of this FN current is determined by the potential of the floating gate electrode that is comprised of the first and second polycrystalline silicon films
13
and
18
. The potential of this floating gate electrode is determined by the coupling ratio of the capacitance of the gate oxide film
12
to that of the ONO film
19
. That is, the coupling ratio of the capacitance of the gate oxide film
12
to that of the ONO film
19
becomes important at the time of electron injection and emission.
Given that the capacitance of the gate oxide film
12
is C
1
and the capacitance of the ONO film
19
is C
2
, the coupling ratio satisfies the relationship of an equation 1 below.
C=C
2
/(
C
1
+
C
2
)  (1)
The capacitance C
2
of the ONO film
19
satisfies the relationship of the following equation 2:
C
2
=&egr;×
S/d
  (2)
where S is the surface area of the ONO film
19
, d is the thickness of the ONO film
19
and &egr; is a dielectric constant.
To increase the potential of the floating gate electrode, the coupling ratio C given by the equation 1 should be increased. To increase the coupling ratio C, the thickness of the ONO film
19
may be reduced or the surface area of the ONO film
19
may be increased as apparent from the equation 2.
If the ONO film
19
becomes thinner, however, the leak current is produced. As a result, the reliability of the ONO film
19
cannot be secured. Further, the surface area of the ONO film
19
depends on the size of the opening of the slits
18
b
. In the formation of the slits
18
b
shown in
FIG. 31
, however, the demanded precision for the slits
18
b
is severer than the one that can be adjusted by the state-of-the-art technology. It is therefore difficult to meet the strict size precision for the slits
18
b
according to the current design rules. This makes it hard to increase the surface are of the ONO film
19
.
As apparent from the above, the use of the conventional fabrication method faces a difficulty in designing miniaturized devices, and cannot provide highly reliable semiconductor devices.
BRIEF SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a semiconductor device which facilitates designing of miniaturized devices and has an improved reliability, and a method of fabricating this semiconductor device.
To achieve this object, according to one aspect of this invention, there is provided a semiconductor device comprising a trench for isolating device regions in a semiconductor substrate; a gate oxide film formed on the device regions; a first polycrystalline silicon film formed on the gate oxide film; a first insulating film for exposing an upper portion of the first polycrystalline silicon film and burying the trench; sidewall spacers comprised of a second polycrystalline silicon film formed on sides of the exposed upper portion of the first polycrystalline silicon film; and an ONO film formed on an entire surface.
In this semiconductor device, a relationship of b≦a=x<c/2 may be satisfied where x is a thickness of the sidewall spacers, a is a distance from a surface of the first insulating film to a surface of the first polycrystalline silicon film, b is a thickness of the second polycrystalline silicon film at a time of formation thereof and c is a distance between adjoining first polycrystalline silicon films.
The semiconductor device may further comprise a second insulating film formed between the

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