Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-02-25
1999-09-21
Brown, Peter Toby
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438199, 438229, 438230, 438231, 438232, 438275, 438303, 438306, H01L 21336
Patent
active
059565918
ABSTRACT:
A method of making N-channel and P-channel devices using separate drive-in steps is disclosed. The method includes providing a semiconductor substrate with first and second active regions, introducing a first dopant into the first active region to provide all doping for a source and a drain in the first active region, driving-in the first dopant to form the source and the drain in the first active region, introducing a second dopant into the second active region to provide all doping for a source and a drain in the second active region after driving-in the first dopant, and driving-in the second dopant to form the source and the drain in the second active region. Preferably, the first dopant is arsenic or phosphorus, the second dopant is boron, and the first temperature exceeds the second temperature by at least 50.degree. C. In this manner, the boron need not be subjected to the higher first temperature, thereby reducing boron diffusion.
REFERENCES:
patent: 4345366 (1982-08-01), Brower
patent: 4757026 (1988-07-01), Woo et al.
patent: 4818714 (1989-04-01), Haskell
patent: 4847213 (1989-07-01), Pfiester
patent: 4978626 (1990-12-01), Poon et al.
patent: 5070029 (1991-12-01), Pfiester et al.
patent: 5169796 (1992-12-01), Murray et al.
patent: 5439834 (1995-08-01), Chen
patent: 5455444 (1995-10-01), Hsue
patent: 5460993 (1995-10-01), Hsu et al.
patent: 5504031 (1996-04-01), Hsu et al.
patent: 5610088 (1997-03-01), Chang et al.
patent: 5614432 (1997-03-01), Goto
patent: 5618748 (1997-04-01), Segawa et al.
patent: 5650341 (1997-07-01), Yang et al.
patent: 5691225 (1997-11-01), Abiko
patent: 5786247 (1998-07-01), Chang et al.
Silicon Processing for the VLSI Era-vol. 3: The Submicron MOSFET, by S. Wolf, published by Lattice Press, Sunset Beach, CA, 1995, pp. 608-611.
Advanced Micro Devices , Inc.
Brown Peter Toby
Holloway William W.
Pham Long
LandOfFree
Method of making NMOS and PMOS devices having LDD structures usi does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of making NMOS and PMOS devices having LDD structures usi, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making NMOS and PMOS devices having LDD structures usi will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-90871